NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?
DK-DEV-AGI027-RA: JTAG chain broken after Nios V Hello, FPGA recovery fails
Hello, I am using the following board and host environment: Board: Agilex 7 FPGA I-Series Development Kit, DK-DEV-AGI027-RA Serial number: 8100604 Quartus Prime Pro: 25.3.1 Host OS: Windows 11 Pro Before this issue, the board was working normally with CXL ED and PCIe designs. Issue summary After successfully running a modified version of the "Nios V Hello" tutorial design (SOF + ELF) on this kit, Quartus Programmer can no longer detect the JTAG chain reliably. "Auto Detect" fails, and the JTAG Chain Debugger reports unknown devices and possible JTAG signal issues. Steps and observations 1. I modified the Nios V Hello tutorial design (SOF + ELF), including pin assignments and power management & SmartVID assignments, to match DK-DEV-AGI027-RA. Programming completed successfully, and I confirmed the expected "Hello" output. After that first run, I attempted to download an updated SOF, but Quartus Programmer "Auto Detect" failed. JTAG Chain Debugger screenshot: Programmer/Debugger log: !Error: JTAG chain problem detected !Error: TDI connection to the first detected device UNKNOWN_00000001 might be shorted to GND !Error: The TCK and TMS connections to the device before the first detected device UNKNOWN_00000001 might have a problem !Info: Detected 2 device(s) !Info: Device 1: UNKNOWN_00000001 !Info: Device 2: UNKNOWN_020D10DD Recovery attempts and results 2. Connected an external USB-Blaster II to J10, set SW8.3 = ON, and completed MAX10 recovery successfully. 3. Set SW8.3 = OFF to attempt FPGA recovery. Quartus Programmer Auto Detect still failed. 4. Loaded the predefined fpga_recovery.cdf and attempted to program AVSTX8.pof, but it failed with: Error(209062): Flash Loader IP not loaded on device 2 Error(209012): Operation failed 5. Set SW8.2 = ON to remove the FPGA from the JTAG chain, then successfully programmed AVSTX8.pof into QSPI. 6. Set SW8.2 = OFF again, but Auto Detect still failed. 7. Removed the external USB-Blaster II and tried the embedded JTAG interface. Auto Detect still failed. Questions. Are there additional recommended steps beyond MAX10 recovery and programming the recovery POF to QSPI (for example, specific switch combinations, a required full power-cycle sequence, or other board-level recovery steps)? If MAX10 recovery completes but JTAG remains broken on both external and embedded JTAG, does this suggest a likely hardware issue (JTAG path, FPGA, or related circuitry) that requires RMA? Is there anything in the Nios V Hello tutorial flow that could plausibly cause this condition (for example, power management settings, pin assignments, or JTAG-related settings)? If needed, I can share additional logs, exact switch settings, and any other diagnostics you recommend. Thanks.
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,Ashling IDE scripted project creation
On Windows, is there a way to script the Ashling IDE project creation (or import an existing project)? I'm trying to clean my project down to the bare minimum for CM/repo purposes (deleting .metadata), and then have an automated way to recreate the project up to the point I can open Ashling RiscFree IDE, point to my (newly recreated) workspace, and then the project is already imported and ready to build, with all my previous settings (include paths, optimizations). Right now, the only way I can get this to work is if I manually click File -> Import and go through that dialog to import my sources from the repo. I need a hands-off way to do this. I looked at the Ashling RiscFree IDE manual, but couldn't find anything.No valid license for Nios processor
I tried to compile example designs on Altera’s websit. If the design includes a Nios processor, I’d get the following error. Do I need to request a separate license patch for Nios processor? Error(23714): Can not generate programming files for your current project because you do not have a valid license. Visit the Intel FPGA Self-Service Licensing Center at https://licensing.intel.com Warning(115005): Unlicensed IP: "Nios V/g General Purpose Processor Intel FPGA IP (6AF7 018C)" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/auto_fab_0/23.4.0/final/1/netlist.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/auto_fab_0/23.4.0/final/1/names.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/root_partition/23.4.0/final/1/netlist.model" Warning(115004): Unlicensed encrypted design file: "/home/alin84/quartus_example/top_restored/hw_g/qdb/_compiler/top/root_partition/23.4.0/final/1/names.model"DE23-Lite + Quartus Pro 25.1 + Nios V/g: no Nios V instance, no JTAG UART
Hi, I’m working on a Terasic DE23-Lite board (Agilex 3 A3CZ135BB18AE7S) using Quartus Prime Pro 25.1, and I’m seeing a runtime debug/service issue that I have not been able to resolve. System details: Board: Terasic DE23-Lite FPGA: Agilex 3 A3CZ135BB18AE7S Quartus Prime Pro: 25.1 CPU in Platform Designer: Nios V/g Project started from the Terasic SDRAM_Test_NiosV / golden_top example USB-Blaster III is detected normally as DE23-Lite [USB-1] What works: quartus_pgm programs the .sof successfully jtagconfig sees the board and FPGA in the JTAG chain Simple RTL-only hardware tests work CLOCK0_50-driven LED blink works KEY0-driven LED test works So basic board programming, raw JTAG visibility, and simple user logic are all working. What does not work: niosv-download fails with: "There are no devices with valid Nios V instance(s)" "ERROR: Failed to generate OpenOCD config file." juart-terminal fails with: "There are no JTAG UARTs available which match the --device and --instance options you provided." In System Console, the following all return nothing: get_service_paths device get_service_paths master get_service_paths processor get_service_paths jtag_debug SignalTap also does not enumerate at runtime and reports that the device needs to be programmed / instance not found, even after compile and program. Important points: The generated Platform Designer system does include Nios V/g debug-related logic and JTAG UART in the generated HDL. The top-level does instantiate the generated nios_system. The QSF includes the Qsys system. The fit report shows SignalTap content present in the fitted image. So this does not look like a missing-instance-in-the-design problem. It looks more like raw JTAG chain works, but no higher-level runtime services enumerate after configuration. One thing I found: In the example golden_top.v, the Nios system clock connection had a typo: .clk_clk(CLOCK1_51)instead of a real clock signal. I corrected that and also tested CLOCK0_50. That did not resolve the no-instance / no-JTAG-UART / no-service-paths issue. Another issue I found and fixed: There was a stale on-chip memory init reference to ram.hex: "Cannot find Memory Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex) C:/fpga/SDRAM_Test_NiosV/ram.hex -- setting all initial values to 0." I removed that stale reference. It did not fix the runtime service visibility problem. Current question: Has anyone seen a case on DE23-Lite / Agilex 3 / Quartus Pro 25.1 where the JTAG chain is visible and programming succeeds, but Nios V instances, JTAG UART, System Console service paths, and SignalTap all fail to enumerate at runtime? I’m looking for guidance on what layer to check next: JTAG service / SLD runtime visibility Agilex 3 user-mode debug exposure board/project configuration settings Quartus 25.1-specific issue anything DE23-Lite-specific in the Terasic example flow Any suggestions would be appreciated. Thanks, Steve
NiosV µC/OS-II TCP-IP debug
Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devkit, so I compiled it for two different Arria10 targets. For both targets, I get the error: [network_init] Failed to NetIF_Start(): (2010). TSE link seems to be OK. Since I'm not experienced with Nios, I'm looking for help to debug it. Thanks
Unable to transmit out of 16550 Compatible UART
Hi I am following the example of the 16550 Compatible UART in the Embedded peripherals IP User Guide and using the provided code I am not seeing any data in the loopback configuration. Software is Quartus Prime Lite 18.1 Any idea or suggestions is greatly appreciated. I'm not sure if I need to configure any registers?NiosV µC/OS-II
Hello, I try to design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I understand that uC-TCP-IP library needs µC/OS-II but this option is not available in bsp editor GUI (only hal and freertos are available). When I try to execute the command from the project README, I have the following error : $ niosv-bsp -c sw/bsp/settings.bsp -qpf=hw/top.qpf -qsys=hw/sys.qsys --type=ucosii --cmd="enable_sw_package uc_tcp_ip" ... 2026.03.11.18:36:31 Warning: Environment variable SOPC_KIT_NIOS2 not set 2026.03.11.18:36:38 Info: Searching for BSP components with category: os_software_element 2026.03.11.18:36:41 Error: BSP type "ucosii" is not valid. Valid types are: * freertos * hal I'm using Quartus Version 23.4.0 Build 79 11/22/2023 Patches 0.70 SC Pro Edition Thank you for your help.NIOS interface to HPS in Agilex 5 for communication.
The question is about having NIOS design interacting with HPS of same FPGA. The NIOS would be created as design partition and imported to the HPS project. My understanding is normally this is done through the FPGA2HPS/HPS2FPGA bridge. How this is implemented in project where the NIOS is imported design partition in the HPS project.
