How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr Barry
Nios V Hardware Interrupt Limitations
Hello, Based on the Nios V Processor Reference Manual and AN 978 Nios V Processor Migration Guidelines, Nios V supports only 16 hardware interrupts, whereas Nios II supports 32. Additionally, the External Interrupt Controller is not available in Nios V. Since Nios II has been deprecated, we are evaluating the transition to Nios V. However, our system requires more than 16 hardware interrupts. Does Intel provide any recommended approach for handling more than 16 hardware interrupts in Nios V? Are there plans to extend this capability in future releases? Best regards.Unable to Download top.par from Stratix 10 SDM Bootloader Design Example
Hello, I am trying to download the top.par file from the following Intel design example page: Stratix 10 FPGA SDM Bootloader for the Nios® V/G Processor Stratix® 10 FPGA – SDM Bootloader for the Nios® V/g Processor Design Example When I click on “Download top.par”, I consistently receive the following error: "The requested URL was rejected. Please consult with your administrator. Your support ID is: 4878817614298363410" This happens across different browsers and systems, and I am logged into my Intel/Altera account when accessing the page. Could you please advise: Whether this is a known issue with the download link If there are any access or permission requirements Or if there is an alternative way to obtain the top.par file Any guidance or a corrected download link would be greatly appreciated. Thank you for your support.Created Free NIOSV IP evaluation license but did not get any license file by email?
Hi ALTERA NIOSV experts, I have created licenses (the free evaluation type) through the Intel Altera Licensing portal for NIOSV-c, NIOSV-g, and NIOSV-m IP types. I get 3 messages saying a license has been created and i can see all the correct fields are filled in on the license form each time. It then says you will get a license by email. But after 2 hours i still have not received anything from Intel-Altera. Is there a problem with this licensing platform ?Is there a time delay between creating a license and actually getting it by email ? Usually this occurs very quickly, but not in this case ! Any suggestions or help much appreciated ! Thanks, Barry
Can the .jic file, which is an FPGA configuration file, include the on-chip memory file of nios ii ?
Hello If I specify the contents (.hex) of the on-chip memory of my Nios II embedded processor design, compile it through Quartus Prime Pro, and use convert programming to create a .jic file, will the on-chip memory contents also be loaded into the .jic file? So, can I just load the jic file into external flash memory via a download cable? Thank you Michael