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ashutoshsriram's avatar
ashutoshsriram
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2 months ago

not able to use multiple niosV cores at the same time

when I run ultiple niosV cores at the same time im not able to acess each of them even though i am able to detect them , i am faced with 

even though detecting gives me 

and i am unable to use the cores likewise

 

this is my file on platform designer 

 

 

Embedded Applications Layer
Nios Architecture
Nios Cpu

7 Replies

  • knithink_Altera's avatar
    knithink_Altera
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    2 months ago

    Hi,


    Looking at the design snapshot shared by the user, it seems that one of the Nios V (uart1_niosv) reset signal is connected to 2 different reset interfaces.

    One reset is coming from the reset bridge IP, which is the reset signal to most of the other IPs in the design.

    On trying to correlate both snapshots, I think the other reset is coming from the debug module reset output of the second core (uart2_niosv).

    Please confirm the same.

    The other Nios V (uart2_niosv) has just one reset connection, which is correctly connected to the reset bridge.

     Assuming the reset is coming from debug module reset output of the second core:

    1. Please follow the description below to ensure debug reset output signal is triggered correctly.
    2. Also ensure that you are resetting the Nios V core with correct polarity.

     

     

  • ashutoshsriram's avatar
    ashutoshsriram
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    2 months ago

    Thank you for your response. I had already tried that configuration as well. However, when I launch the Ashling debugger, it still reports that only 1 HART is available, even though both Nios V cores are visible in the JTAG scan chain and are detected correctly.

    Because of this, I am unable to select or debug the second core. If there are any additional settings or requirements specific to multi-core Nios V systems that I may have missed, I would appreciate any suggestions.

    • knithink_Altera's avatar
      knithink_Altera
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      2 months ago

      Hi,

      There are no specific recommendations or methods for Nios V multi core design reset mechanism.

      Any working reset mechanism can be used.

       

      We have our Lockstep Example Design where we are using 2 Nios V cores.

      The Nios V/m core acts as the supervisor.

      The Nios V/g core has the Lockstep enabled.

      The design was released in 25.3.1. Following is the link for the same- https://github.com/altera-fpga/agilex7f-nios-ed/tree/rel/25.3.1/agf014ea-dev-devkit/niosv_g/lockstep 

      compiled design package- https://github.com/altera-fpga/agilex7f-nios-ed/releases/download/25.3.1/agilex7_niosv_g_lockstep.zip 

      The Nios V/g core reset is connected to a PIO output. The PIO is driven by Nios V/m core. The Nios V/m core toggles the PIO value which resets the Nios V/g core.

      Nios V/m -> Write value 1 to PIO -> PIO output connected to Nios V/g reset input -> Nios V/g reset input is high which resets the core -> After some delay, write 0 to PIO via Nios V/m -> The reset input to Nios V/g goes low.

      The reset of the Nios V/m core is connected to the common reset signal that the remaining IPs are connected to. (The PLL locked output is used for the reset).

      May i know why uart1_niosv reset input is connected to 2 reset ports (reset bridge and debug reset output from other Nios V core)? The 2 resets may be conflicting and hence causing the core to remain in reset state. Is this specific requirement?

      If not, i suggest you just connect the reset to a single reset port.

      You can also explore the reset methodology in the above mentioned lockstep solution.

  • ashutoshsriram's avatar
    ashutoshsriram
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    2 months ago

    That was the wrong qsys file the original qsys file had the reset port connected to the main clock reset only, was there any specific reason that you had to use the pio from niosv/m as a reset for the noisv/g? Can multiple softcores be connected in the same architecture? As connecting both nios through a reset bridge and normally to the clock reset didnt work and gave the same error.

    • tehjingy_Altera's avatar
      tehjingy_Altera
      Icon for Regular Contributor rankRegular Contributor
      2 months ago

      Hi All

       

      I would like to share that I have successfully tested version with Quartus 26.1, and it is working as expected.

      In my design, I have two NiosV instances instantiated in my design, and the Ashling IDE is able to detect and select either instance without any issues.

       

      Regards

      tehjingy

  • LiangYuG_Altera's avatar
    LiangYuG_Altera
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    2 months ago

    Hi ashutoshsriram​ 

    Can you try accessing the core using OpenOCD (niosv-download -o)?
    The failing Ashling version (you had) is exactly the same v25.2.1 (version dated 9th May 2025) reported in the KDB.

    Why does Ashling* RiscFree* IDE for Altera® FPGAs detect Core 0 only in a Nios® V processor multicore system? | Altera Community - 349124 

    If the OpenOCD is able to select the different core, try downloading the standalone Ashling RiscFree IDE + Quartus Programmer in Quartus Standard 24.1 (Link).

    • The IDE is 25.1.1 (version dated 31st Jan 2025), which doesn't have this issue.
    • No new license is needed.

    Since your Ashling version is v25.2.1, my guess is that you are using the Ashling IDE from Quartus Standard 25.1 installation package.

    Thus, switch to a different Ashling version might help.

    Regards,
    Liang Yu