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sonycman's avatar
sonycman
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1 month ago

Dual Port Nios V BSP error

I've created a Nios V qsys with dual port onchip memory in Quartus Pro 26.1

True dual port, first port connected to instruction manager, second - to data manager.

Base addresses automatically assigned the same to both.

 

But i'am unable to create the BSP due to memory regions overlapping error!

Of course the addresses are same - its the same physical onchip memory!

 

Any solytion, please?

Regards, Vlad.

Embedded Applications Layer
Nios Cpu

3 Replies

  • SteveK_Arrow's avatar
    SteveK_Arrow
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    1 month ago

    Hi Vlad

    You can manually select a different address for the s2 port of the dual port RAM that does not overlap the address for port s1. This will resolve the issue. Double click in the base column  of the s2 port to modify the address. I built an example to verify this and have inserted a few snapshots below. 

     

     

    • sonycman's avatar
      sonycman
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      1 month ago

      Yes, but would that be working solution regarding software, linker would see those memories as different, but those are the same actually! It must be just single memory for the compiler/linker to utilize it properly.

      It needs to be tested in practice, thank you for suggestion.

       

      There might be another solution - to generate BSP for common single port memory, and then change just the memory to dual port and regenerate hardware leaving the BSP intact. A workaround, kind of...

       

      • SteveK_Arrow's avatar
        SteveK_Arrow
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        1 month ago

        The instruction and data masters of the Nios have their own memory maps, so it should be legal to connect them to two different memories that have the same base address. I modified the design to use two separate single port memories (with the same base address). The instruction master connected to the first memory and the data master to the second. I got the same error in the bsp editor.

        Even though my previous suggestion passed through the tools without error, it would cause a problem since the bsp editor might assign linker sections that actually overlap on the physical memory itself.

        The workaround that you suggested might be ok. It would have to be tested.

        I will open a case with the factory to see if i can get an explanation regarding the bsp editor errors.