AshlingRISCFree IDE Build system: 'source directory does not appear to contain CMakeLists.txt"
Hello Altera Gurus, I am now having much trouble building my projects with the AshlingRISCFree IDE using a NIOSV/m processor on a MAX10 FPGA targeted at a MAX10 Development kit. I am using Quartus Standard edition 25.1 on a Windows 10 PC. The process i am following is this: I created an FPGA top level System Verilog file for a new MAX10 Project. created a Qsys Platform which has a NIOSV/m processor connected to a onchip RAM for program storage and a onchip RAM for the DMA data. Added one mSGDMA engine for transmit data operations Added a second mSGDMA engine for receivedata operations Added two RAM onchip memories for the DMA decsriptors and wired up everything created the address map and interrupt mapping saved and generated the Qsys platform In the top level SV file is loopback the Tx -> RX for the two mSGDMAs Used the niosv-bsp-editor in a niosv console to created a BSP using the Qsys sopcinfo file Generated the BSP, created a simple C main application to configure the mSGDMAs and NIOSV/ m processor etc. Imported both the HAL_BSP and HAL_APP folders using: 'Import NIOS-V CMake Project... In the AshlingRSICFree IDE i can successfully run a 'Build all' and compile the HAL_BSP. BUT When i select the hal_app folder and try to build the Project i get these error messages: 17:37:20 Buildscript generation: hal_app::Default in D:\VAREX_mSGDMA_Eval\software\hal_app\build\Default cmake -DCMAKE_EXPORT_COMPILE_COMMANDS:BOOL=ON -G "Unix Makefiles" "D:\\VAREX_mSGDMA_Eval\\software\\hal_app" CMake Warning: Ignoring extra path from command line: "D:\VAREX_mSGDMA_Eval\software\hal_app" CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. Specify --help for usage, or press the help button on the CMake GUI. Problems : Description Resource Path Location Type CMake Error: The source directory "D:/VAREX_mSGDMA_Eval/software/hal_app" does not appear to contain CMakeLists.txt. hal_app de.marw.cdt.cmake.core.internal.CMakeErrorParser CMake Problem cmake exited with status 1. See CDT global build console for details. hal_app de.marw.cdt.cmake.core.internal.BuildscriptGenerator Buildscript Generation Problem Looking at the hal_bsl folder i can see the CMakeLists.txt is present, it is not present (automatically anyway) in the hal_app folder. I assume it would be if it was part of the BSP generate flow, but it ins't there so i assumed it shouldn't be there (in the hal_app folder i mean). Even if i add it manually then try to do a project build again i then see an error message saying the CmakeCache.txt file has not been created. This seems like a big tools flow mess to me. The Project is automatically setup to use a CMake Compile and CMake Build flow. But its not working. I am trying to use the AshlingRISC IDE GDB Debugger to load my ELF file to the NIOSV processor to allow me to debug my project, but of course because i can't even build it this is impossible. I have tried using niosv cli commands to build my ELF file ...and they seem to work, which means the AshlingRISC IDE is the culprit in the failed IDE build process: Here are my NIOSV cli commands : mSGDMA Test: $ niosv-app --bsp-dir=D:/VAREX_mSGDMA_Eval/software/hal_bsp --app-dir=D:/VAREX_mSGDMA_Eval/software/hal_app --srcs=D:/VAREX_mSGDMA_Eval/software/hal_app/msgdma_loopback.c $ cmake -S D:/VAREX_mSGDMA_Eval/software/hal_app -B D:/VAREX_mSGDMA_Eval/software/hal_app/build -G "Unix Makefiles" -DCMAKE_BUILD_TYPE=Debug $ make -j4 -C D:/VAREX_mSGDMA_Eval/software/hal_app/build After i try and fail to do a project build i can also no loner clean this project, it gets stuck in red with the same error. The only way i can get it back to the start state is : File -> Restart ...this is not great !! Does anybody know why i get these errors and how to fix them please ? : Here i have also linked to an older post here in the knowledge base Claiming that "This problem is fixed starting with the Intel® Quartus® Prime Pro Edition Software version 21.4. and later". This appears to be NOT the case though :) Why does CMake Error: The source directory "<project_directory>/intel_niosv_m_0_EXAMPLE_DESIGN" does not contain CMakeLists.txt. when compiling the Nios® V processor application in Command Line Interface? | Altera Community - 338917 NOTE: I have attached 3 screenshots, 2 show the output from the NIOSV CLI when i run the 3 compile commands. The third one shows what happens when i try to load the ELF file which was created after the 3 Compilation steps run to completion. It looks like the GDB debugger detects the NIOSV/m processor (the 1 hard message) and then promptly crashed during part of the boot process. Does anybody have any ideas about why that might be and what is going on please ? Thanks for any help, Dr Barry HAshling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
NIOS2 filesystem support
We have a system running on NIOS 2 processor with Cyclone5 FPGA and ecos RTOS. We are planning to remove the OS dependency and convert the application to baremetal. Already JFFS filesystem and FIS filesystem are being used in the application. Is there any filesystem libraries that can be used in baremetal? Files are having read and write access. Any specifc links to some examples of the usage of the same in NIOS 2 processor?eCoS OS throws execption when freeing memory
We have a firmware applicaiton that makes use of eCoS RtoS and NIOSII core. We have a logic that we first allocate memory dynamically and then if required delete the previous allocated memory and allocate bigger one - this step goes on until requirement is met. But we are observing exception from eCos during execution of these steps - in other words say when we ietrate over the above logic for 7th time, while freeing memory that time we get exception but allocation which is done prior to free succeeds: ExceptionHandler(data = 0x0, exception_number = 0x0, info = 0x017FFF74) cyg_hal_exception_handler(regs = ???) _software_exception_handler(asm) exception Cyg_Mempool_dlmalloc_Implementation::free(this = 0x0158AD40, mem = ???, unnamed = ???) Cyg_Mempolt2<Cyg_Mempool_dlmalloc_Implementation>::free(this = 0x0158AD40, p = ???, size = ???) free(ptr = ???) npfree(ptr = 0x017136A0) vf_free_buffer(buffer = 0x017136A0, size = 0x0007E000) vfwrite_locked(buf = 0x016956B0, size = 0x1, items = 0x0400, vfd = 0x01696F10) vfwrite(buf = 0x016956B0, size = 0x1, items = 0x0400, vfd = 0x01696F10) getfile(asm) WriteFileToFlash(notUsed = 0x0) ecos_thread_entry(entry = 0x0D) Cyg_Scheduler_Base::get_current_thread(inline) Cyg_Thread::self(inline) Cyg_Thread::exit(inline) Cyg_HardwareThread::thread_entry(thread = 0x01262448) end of frame Can anyone please let me know why exception is thrown at later part of step process execution and what the fix for this issue?How to reduce ROM/RAM requirements for a NIOSV Compact CPU Platform?
Hello ALTERA NIOSV Experts, I am trying to create a system in Quartus Platform Designer which has the following components: A 1G Tri mode ethernet IP (with 32 bit AVALON-ST TX/RX interfaces using minimum sized FIFOs) A RS 232 UART with no FIFO A couple of small FIFOs using AVALON-ST interfaces for data in and out of Platform via Conduits A NIOSV Compact CPU A JTAG UART ROM for NIOSV RAM for NIOSV My questions are about how to reduce the ROM (for the NIOSV compacts program) and RAM to the minimum amount. I am trying to shoehorn this all into a MAX10 FPGA ( Altera Max 10 part number 10M08SAU169I7G). When i build the BSP for this platform, with a "Hello World" program, it seems to need around 128 Bytes of ROM and several KBytes of RAM. Why is the program so large ? I expect it has to do with the BSP adding in drivers for all the Platform IP and it is getting bloated. What tactics are available for me to use in the Ashling RISC FREE IDE which i am using to create my BSP and/or Platform Designer to reduce the program size ? The FPGA i am trying to use only has around 48 K Bytes of RAM available in total ...so maybe this is not possible and i need a bigger FPGA of course ! Thanks for your help, Dr Barry
Nios V: niosv-download reports "no harts found" on Agilex 5 board
I am seeking for ideas with the following issues I have on agilex 5. I want to test a very basic example "hello world" on the board. However, I got a problem on downloading the elf file. My sof file includes a noisv processor and it's successfully download to the board. I can run the command jtagconfig and the following output shows the USB Blaster. The .elf file is generated successfully through the cmake command. However, when I execute the command niosv-download.exe app.elf --go, the follwing error will be outputted. My design in Platform Designer is attached.Replacement for altera_avalon_new_sdram_controller in Quartus Prime Standard 24.1 (Cyclone V)
Hello, I am currently trying to work with Nios V, and I would like to migrate my previous project from Quartus Prime Standard 18.1 to Quartus Prime Standard 24.1. However, I noticed that the altera_avalon_new_sdram_controller IP is no longer supported in 24.1. The external memory device I am using is IS45S16100H, and the FPGA device is Cyclone V: 5CEBA7. Could you please advise if there is any recommended replacement IP or solution for this case? Thank you very much for your help!
