Maybe my question is naive, but do you mean I need an external PHY? I remembered, while reading your answer, that I disabled MDIO.
TSE led_link signal is set to '1'. When I read the PCS Configuration Registers (address 0x200) and I obtained 0xFF for the control register, 0x3F for the status register (it confirms that link status is valid), and 0x1 for the phy_identifier register.
My TSE configuration is:
10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS
Can you please enable MDIO. The design will need external PHY. The uCOSII TCP IP stack with design support Marvell 88E2110 SGMII PHY. Can you provide information on the external PHY, please share the complete log message. If you have different external PHY then you will need to write your own uCOSII driver for external PHY .
I don't have an external PHY, can it not work with an internal one? In the reference design, the serial link comes from TSE, it does not export a GMII interface. I think I missed something.
This is the complete log:
juart-terminal: connected to hardware target using JTAG UART on cable
juart-terminal: "DE5 on localhost:1315 [1-1.3]", device 1, instance 0
juart-terminal: (Use the IDE stop button or Ctrl-C to terminate)
[crt0.S] Setting up stack and global pointers.
[crt0.S] Clearing BSS
[crt0.S] Calling alt_main.
[alt_main.c] Entering alt_main, calling alt_irq_init.
[alt_main.c] Done alt_irq_init, calling alt_os_init.
[alt_main.c] Done OS Init, calling alt_sem_create.
[alt_main.c] Calling alt_sys_init.
[alt_main.c] Done alt_sys_init.
[alt_main.c] Redirecting IO.
[alt_main.c] Calling C++ constructors.
[alt_main.c] Calling atexit.
[alt_main.c] Calling main.
[main] Main Task TOS: 0x4f888
Print the value of System ID
System ID from Peripheral core is 0xFACECAFE
[uc_main_task]
[uc_main_task] ==============================================================
[uc_main_task] uC/TCP-IP Setup
[uc_main_task] ==============================================================
[uc_main_task] TSE MAC base: 0x212000.
[uc_main_task] Rx csr name: /dev/sys_tse_msgdma_rx_csr.
[uc_main_task] Tx csr name: /dev/sys_tse_msgdma_tx_csr.
[uc_main_task] INFO: Initializing network stack.
[network_init] Failed to NetIF_Start(): (2010).
[uc_main_task] INFO: Initializing network stack: Failed.
The design needs external Ethernet PHY as A10 FPGA device does not on chip Ethernet PHY. So for this design (SGMII OR GMII) interface the target board needs external Ethernet PHY. I hope this clarifies your questions. please let me know if you have any other questions.
I have some difficulty to understand. In the case of an external PHY, you're supposed to export (S)GMII port, here it is the serial port which is exported. On our board, we already use TSE, without an external PHY, for UDP transfers.
This is how data movement happens in the A10 Nios V+TSE SGMII based solution that we have released
This is the port mapping and pin assignment:
As you can see, it is a serial output from the TSE which goes to on-board SGMII PHY and then to the link partner via RJ45 Cable.
Regarding your statement:
On our board, we already use TSE, without an external PHY, for UDP transfers.
Questions:
Without PHY, where is the UDP data going to once it is sent out of TSE (MAC+PCS/PMA)?
What is the interface (RGMII or SGMII) and link partner?
Since it is UDP, there is no handshake and there is no way to get to know if packet reached the link partner unless some application is running on the link partner.
What is running on the link partner?
I was assuming that you have not modified our design and software and using it as is.
Hence we are stressing on the PHY part.
Looking at your statement on UDP transfers, i believe you have your own software?
Because our software solution only supports TCP and not UDP.
There is a way of not using the on-board PHY module.
The A10 board has 2 SFP+ interfaces via which ethernet data can be Tx/Rx.
Can you please let us know if you have modified our design and software to use these ports?
Overall, I would like to understand what all modifications have been done on top of our A10 Nios V + TSE solution both on the hardware design as well as on the software.
New Contributor
