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antoineb's avatar
antoineb
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1 month ago

NiosV µC/OS-II TCP-IP debug

Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devki...
Embedded Applications Layer
Nios Cpu
antoineb's avatar
antoineb
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1 month ago

Hello,

Sorry for my late answer.

I have some difficulty to understand. In the case of an external PHY, you're supposed to export (S)GMII port, here it is the serial port which is exported. On our board, we already use TSE, without an external PHY, for UDP transfers.

Maybe we can continue this discussion by email.

Best

knithink_Altera's avatar
knithink_Altera
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26 days ago

Hello,

This is how data movement happens in the A10 Nios V+TSE SGMII based solution that we have released

This is the port mapping and pin assignment:

As you can see, it is a serial output from the TSE which goes to on-board SGMII PHY and then to the link partner via RJ45 Cable.

Regarding your statement:

On our board, we already use TSE, without an external PHY, for UDP transfers.

Questions:

  1. Without PHY, where is the UDP data going to once it is sent out of TSE (MAC+PCS/PMA)?
  2. What is the interface (RGMII or SGMII) and link partner?
  3. Since it is UDP, there is no handshake and there is no way to get to know if packet reached the link partner unless some application is running on the link partner.
  4. What is running on the link partner?

I was assuming that you have not modified our design and software and using it as is.

Hence we are stressing on the PHY part.

Looking at your statement on UDP transfers, i believe you have your own software?

Because our software solution only supports TCP and not UDP.

There is a way of not using the on-board PHY module.

The A10 board has 2 SFP+ interfaces via which ethernet data can be Tx/Rx.

Can you please let us know if you have modified our design and software to use these ports?

Overall, I would like to understand what all modifications have been done on top of our A10 Nios V + TSE solution both on the hardware design as well as on the software.

Thanks.

  • antoineb's avatar
    antoineb
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    24 days ago

    Hello,

    In other projects, I use TSE in 1000Base-X/SGMII PCS only, for 1G ethernet, and 1G/10GbE and 10GBASE-KR PHY for 10G ethernet. The PHY serial link is directly connected to an SFP or QSFP port. 

    We use a VHDL module for UDP, IP and MAC layers connected to GMII port of the TSE. For communication, we use IPBus protocol, with associated software on the partner, for gateware configuration (UDP but with a kind of handshake) and UDP streaming for high speed data acquisition (10G). The ethernet link is working very well. 

    On the reference design, I only modified the pinout to match my board(s) (serial link to SFP/QSFP) as I don't have the hardware design kit. About NIOSV software, I didn't modify anything. I only mentioned other projects to confirm that TSE is working without an external PHY.

    Currently, for the software part of our projects, we use IPbus software for slow control and homemade software for high speed acquisition. We are also doing some tests with DPDK.

    I think that the problem is purely a software problem. Is there someting I have to "skip" to match my configuration?

    Thanks.

     

    • knithink_Altera's avatar
      knithink_Altera
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      23 days ago

      Hello,

      The current solution tries to configure the on board 88E1111 SGMII PHY automatically as soon as the elf file is downloaded.

      As you mentioned that the pin configurations are changed, the error message that you are seeing is valid. The pin configurations was for SGMII PHY configuration.

      We doe not support SFP/QSFP configuration.

      • antoineb's avatar
        antoineb
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        23 days ago

        Hello,

        Ok, so do you think it would be easy to make it compatible? Is it just skipping the configuration of the external PHY or is it more complex?

        Thanks