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antoineb's avatar
antoineb
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5 months ago

NiosV µC/OS-II TCP-IP debug

Hello, I am trying design a NiosV program with TCP/IP based on this example design: Arria® 10 FPGA – Simple Socket Server for the Nios® V/m Processor Design Example I don't have the proposed devki...
Embedded Applications Layer
Nios Cpu
AvinashTh_Altera's avatar
AvinashTh_Altera
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5 months ago

No worries.

We have seen these error messages in our internal testing; here are some details:

This error message means device initialization failed. This can happen due to following reasons:

  • mSGDMA open failures
  • Memory / buffer allocation failures
  • Individual TX/RX descriptor init/add failures
  • PHY / MDIO / link failures
  • MAC-level failures
  • Descriptor system failure
  • MAC Tx/Rx enable failures

So, we suspect it has something to do with the PHY/MDIO init. and linkup- PHY / MDIO / link failures

As we do not have enough information on what PHY the A10 targets have and what are the corresponding MDIO and PHY init sequences.

Questions:

  • What are the PHYs on the your A10 targets?
  • What is the TSE and MDIO configuration in the design?
  • Since it is mentioned "TSE link seems to be OK", can we read the PHY IDs? 

Please let me know if you have any questions. Look forward to hear from you. thanks

  • antoineb's avatar
    antoineb
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    5 months ago

    Hello,

    Maybe my question is naive, but do you mean I need an external PHY?  I remembered, while reading your answer, that I disabled MDIO.

    TSE led_link signal is set to '1'. When I read the PCS Configuration Registers (address 0x200) and I obtained 0xFF for the control register, 0x3F for the status register (it confirms that link status is valid), and 0x1 for the phy_identifier register.

    My TSE configuration is:

    • 10/100/1000 Mb Ethernet MAC with 1000BASE-X/SGMII PCS
    • Use internal FIFO
    • Transceiver type GXB
    • Enable MAC 10/100 half duplex support
    • Include statistics counters
    • Align packet headers to 32bit
    • Enable magic packet detection
    • Enable SGMII bridge
    • Enable transceiver reconfiguration


    Thanks  

  • antoineb's avatar
    antoineb
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    5 months ago

    Also, I'm surprised that there is no transceiver PHY reset controller implemented in the .qsys module. Can it be a reset or initialization problem?

    Thanks