Correct way to use mSGDMA with a NIOSV/m processor on a MAX10 FPGA

Greetings Fawaz, Sorry for the delay in replying to your question. I have been battling away trying to get a Triple Speed Ethernet IP core to work in a MAX10 Development kit. This design uses the two mSGDMA engines that are now working, thanks for your help on that DMA area. But i am really stuck on getting a NIOSV/m processor with software to run Ethernet Frames from an ALTERA TSE. 
My setup is as follows:

MAX10DevKit Design :

NIOSV/m + Tx mSGDMA -> TSE  Transmit [SMALL 1G MAC configuration] <- TSE Receive <- Rx mSGDMA 

 RaspberryPI5 <=> Ethernet <=> MAX10 Dev Kit

I have software to initialise both the MARVELL 88E1111 PHY and the TSE in 1G Small MAC Mode

The software uses interrupts as before the Tx mSGDMA and the Rx mSGDMA and this is working because it uses the same approach as my other design which has the mSGDMA loop back working uising two mSGDMA Engines. One configured as Tx mSGDMA :: AVALON-MM -> AVALON-ST ---> AVALON-ST -> AVALON-MM -> Rx:mSGDMA 

What i see is the MARVEL 88E1111 PHY doing  auto negotiation with a RaspberryPI5 and saying LINK UP

But when i try to send any Ethernet frames (i am sending Frames with a IPv4 + TCP Payload), the first thing my software tries to send is a TCP 3 weay handshake, so from the MAX10 FPGA should send a IPv4 + TCP packet with SYN flag set. On the RaspberryPI 5 i use WIRESHARK to detect packets and i never see any packet being sent by the TSE.

If you could help me figure out why the TSE is not working i can send you my entire project (i am using Quartus Lite 25.1 at the moment) as a 7ZIP file to an email address perhaps ? I don;t think i can attach such a larger file to this post can i!

Best regards, Dr Barry H