gdb server problem when debugging
Hello, I'm running Quartus12.0sp2 on a windows 11 computer and I want to use the nios 2 eclipse tools to build, run and debug. Building and running works, but I encounter a problem with debugging via usb blaster. I get the error message 'Error starting gdbserver - see console for details'. If I start nios2-gdb-server.exe manually, I get the error message that two .dll files are missing: 'jtag_client.dll' and 'cygwin1.dll'. Both are present in some subfolders of c:/altera/12.0sp2. This behaviour does not change when I start eclipse or gdbserver from the NiosII command shell. Funnily, there is also a file 'nios2-gdb-server-fs2.exe' in the installation path, which seems to run. I tried tricking, by renaming this file into 'nios2-gdb-server.exe'. If I do so, the error message disappears, but the debugging process stops when trying to download the .elf file, at the step 'Launching: Stop processor if running'. I found an old discussion about a similar problem in the forum: Win7-Problem with NIOS-II debugger, can't start gdbserver | Altera Community - 224719 but there's also no clear solution for me. Has anyone else encountered a similar problem? Or can anyone explain what's the difference between 'nios2-gdb-server.exe' and 'nios2-gdb-server-fs2.exe'? Or does know where I have to change a Path such that gdb-server can find the .dll files? I'm quite lost and would appreciate any help. Thanks, Timo
LPDDR4 not available in NIOSV/g linker script - Agilex-5, Quartus 26.1 Pro
Hello, I have a simple design for Agilex 5, using NIOS V/g and EMIF IP with LPDDR4 memory. I have the NIOS V instruction and data manager ports connected to the EMIF IP. Design compiles Ok. But when I create a BSP, in the linker section, there is not a memory device for the LPDDR4. In this thread, a similar problem seems to be mentioned - issue-with-bsp-creation-for-nios-vm-using-lpddr4-on-agilex-5-quartus-24-1--24-3 Does it mean that Address Span Extender IP must be used in order to have the LPDDR4 show in the linker script section, as an available memory device?
NIOS V: Systick based timeouts not available when using internal timer
Hello, We are using Quartus 25.1 Standard. I came across something, which I would consider a but in the BSP generated HAL files, or at least a major limitation in the usage of NIOS V. System Setup: NIOS V + JTAG UART NIOS V in internal Timer as Sys_clk_timer BSP Setting: Problems: The JTAG UART drivers have a timeout functionality based on the systick interrupt to avoid getting stuck, in case there is not JTAG UART connected, so the internal buffer fills up. --> see altera_avalon_jtag_uart_timeout() This used to work fine with: NIOS II Setup (using external Timer) NIOS V Setup with external Timer block as sys_clk_timer But when using the NIOS V internal as sys_clk_timer the JTAG UART timeout does not trigger and when calling alt_printf it gets stuck in altera_avalon_jtag_uart_write /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) Analysis When I check the initialization routine of the JTAG UART altera_avalon_jtag_uart_init by stepping through with the debugger, I realize, the alarm is not setup: /* * No OS present: Always wait for data to be removed from buffer. Once * the interrupt routine has removed some data then we will be able to * insert some more. */ while (out == sp->tx_out && sp->host_inactive < sp->timeout) This is because the alt_ticks_per_second() returns 0 During the main() function alt_ticks_per_second() is correctly set to 10 (which is my setting from the BSP) The root cause, is the initialization order in alt_sys_init() within the generated alt_sys_init.c file: void alt_sys_init( void ) { ALTERA_AVALON_TIMER_INIT ( NIOS_SUBSYSTEM_TIMER_0, nios_subsystem_timer_0); ALTERA_AVALON_JTAG_UART_INIT ( NIOS_SUBSYSTEM_JTAG_UART_0, nios_subsystem_jtag_uart_0); ALTERA_AVALON_SPI_INIT ( NSC3_SUBSYSTEM_0_ADC_SPI, nsc3_subsystem_0_adc_spi); ALTERA_AVALON_SYSID_QSYS_INIT ( NIOS_SUBSYSTEM_SYSID_NIOS, nios_subsystem_sysid_nios); ALTERA_AVALON_UART_INIT ( NIOS_SUBSYSTEM_UART_IP, nios_subsystem_uart_ip); INTEL_NIOSV_M_INIT ( NIOS_SUBSYSTEM_INTEL_NIOSV_M_0, nios_subsystem_intel_niosv_m_0); } _alt_tick_rate is initalized to 0 per default and gets set duing alt_sysclk_init(), called from the INTEL_NIOSV_M_INIT Macro As seen above. The INTEL_NIOSV_M_INIT Macro is called last within alt_sys_init. Hence all other modules do see _alt_tick_rate = 0. Hence assume there is no sys tick timer present. Hence all sys tick based alarms are disabled. NOTE: The ALTERA_AVALON_TIMER_INIT Macro is called first. Which appears to be correct IMHO, so the Timer module works as sys tick timer @ Altera: Please advise on this issue. Is there any possibility to change the alt_sys_init initialization order? best regards Fabian
Ashling RISC Free IDE fails to download ELF file
Hello ALTERA NIOSV Experts, I have been trying to execute an application using a NIOSV CPU with the Ashling RISC Free IDE. The problem is that when trying to download the elf file to a MAX10 ALTERA Development board i see an error message saying that the AShling IDE cannot determine the JTAG clock speed. I have added a Screen shot showing this event. Can anyone please suggest a solution to try ? I am currently using an ALTERA USB Blaster to connect but i have just ordered a USB Blaster II as i believe that can connect at faster clock speeds and is also more reliable. Thanks for any help,
Ahsling RiscFree IDE 25.1.1: Unresolved inclusion
Hello, I'm making Nios V test project for Agilex 5 (Arrow AXE5000 Devkit), following instructions in AN 985 Nios V Processor Tutorial. It works basically, I can download and run Nios application on the target. Source window is marking all include files as "unresolved" although the project compiles fine. I can manually add links to all missing includes (most from /bsp/inc folders, some from riscfree/toolchain/riscv32-unknown-elf) to the app tree to resolve the issue. But apparently there's something wrong with the import Cmake project flow. Am I missing a step in the instructions? Regards FrankUnable to transmit out of 16550 Compatible UART
Hi I am following the example of the 16550 Compatible UART in the Embedded peripherals IP User Guide and using the provided code I am not seeing any data in the loopback configuration. Software is Quartus Prime Lite 18.1 Any idea or suggestions is greatly appreciated. I'm not sure if I need to configure any registers?NIOS does not start after SW download (timing issue?)
Hi, Recently I got an old Arria V design to update. It is in Quartus II 15.0 containing the following main components (in Qsys design): NIOS II soft processor 2x UniPHY DDR3 RAM controller (soft version, not hard), 72 bit wide data running at 400MHz clock (800Mb/s) 2x Triple Speed Ethernet with 4x SGDMA The design uses only 40k ALMs out of 190k so it fits well but I have timing issues (slack) on pll_afi_clk for one or both DDR3 controllers. I can reduce it by a lot of fine tuning on synthesizer and fitter settings but when I change a bit in the design timing results go wrong and tuning has to be started again. Both FW and SW are downloaded to SRAM by ByteBlaster. I found when the slacks are big (>0.1ns) NIOS never starts after downloading the SW. When it is small or completely eliminated, NIOS starts in most of the cases (but not always). Is this normal for such a design, or am I doing something wrong? I have never seen such behaviour before. Can this timing issue affect the NIOS processor on such a way or should I search in another direction to solve the problem?
Nios V license
Hi, I need to apply Nios V free license, but in FPGA Self Service Licensing Center, I got error all the time, I signed in successfully, but it says "You do not currently have access to this site" always, as shown in the attached figure. Please help fix this issue, or is there other way to get the license? Thanks.
