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Cyclone 10 GX Nios V Ethernet Ping Issue - UC/TCP-IP Error 20012 and TSE/mSGDMA Debugging ;
Hello , I am developing Ethernet communication on a Cyclone 10 GX FPGA using Nios V/m, the Triple-Speed Ethernet (TSE) IP, msgDMA, a Marvell Alaska 88E1111 PHY, UC-OS-II, and the recommended UC-TCP-IP software components. I am using the recommended UC/TCP-IP .c and .h source files, but I am facing an initialization error before I can complete ping testing. Hardware/software configuration: FPGA: Cyclone 10 GX, Processor: Nios V/m at 50 MHz, Quartus Prime Pro: 26.1.0, Ethernet: TSE with TX/RX mSGDMA, PHY: Marvell Alaska 88E1111 over SGMII, Network stack: UC/TCP-IP, RTOS: UC/OS-II, Board IP: 10.0.0.2/24, PC-to-board ping: Not working Current initialization error The network initialization fails at: NetSock_Init(&err); The returned error is: NET_SOCK_ERR_INIT_CONN_REQ_FAULT (20012) I am using the recommended MicroC/TCP-IP source files with MicroC/OS-II. Before calling NetSock_Init(&err), the following initialization functions execute successfully: Net_InitDflt(); NetCtr_Init(); NetStat_Init(); Net_KAL_Init(); NetTmr_Init(); NetBuf_Init(); NetConn_Init(); NetMgr_Init(&err); NetICMP_Init(&err); NetIP_Init(&err); NetIGMP_Init(); NetUDP_Init(); NetTCP_Init(&err); After these initialization functions complete, I call: NetSock_Init(err); While debugging the recommended KAL implementation, I found that semaphore creation fails inside NetSock_Init(): p_sem = OSSemCreate(0u if (p_sem == (OS_EVENT *)0) { *p_err = RTOS_ERR_CREATE_FAIL; return (handle); } The eighth call to OSSemCreate(0u) specifically within NetSock_Init() returns NULL. The preceding calls return valid semaphore pointers. OS_MAX_EVENTS = 60 OS_LOWEST_PRIO = 80 Additional debugging information – MDIO and PHY detection I have also verified MDIO access to both the internal PCS and the external Marvell Alaska 88E1111 PHY. MDIO space 0: Internal PCS registers. MDIO space 1: External Marvell 88E1111 PHY registers. I can successfully read the registers from both spaces. The external PHY identification registers return PHY ID1 = 0x0141 and PHY ID2 = 0x0CC2. This confirms that I can access the internal PCS and identify the external PHY through MDIO. However, the complete Ethernet packet path and ping communication are not yet verified. TSE MAC debugging : I have verified access to the TSE MAC registers and checked the MAC configuration registers, including COMMAND_CONFIG, MAC address registers, frame length, pause settings, and inter-packet gap. TX/RX mSGDMA debugging: I have separate TX and RX mSGDMA controllers, descriptor memory, and descriptor prefetchers configured in Platform Designer. TSE: 0x00112000, TX mSGDMA CSR: 0x00112480, RX mSGDMA CSR: 0x001124A0, TX descriptor prefetcher: 0x00112440, RX descriptor prefetcher: 0x00112460, Descriptor memory: 0x00110000 I have verified descriptor-memory read/write access using test patterns. However, I have not yet confirmed that complete TX and RX packet transfers work correctly. I need guidance on validating the descriptor format, buffer addresses, descriptor ownership, DMA status registers, and completion/error status. I would also like to know the recommended procedure for validating TX and RX independently before integrating them with the TCP/IP stack. My current blocking issue is MicroC/TCP-IP initialization error 20012 (NET_SOCK_ERR_INIT_CONN_REQ_FAULT). During debugging, I found that the eighth OSSemCreate(0u) call within NetSock_Init() returns NULL, causing semaphore creation to fail. I would like to understand why semaphore creation fails even though the recommended networking source files are being used. Thank you,
Questions About GSFI, QSPI Flash XIP Boot, and HAL API Support
I am currently using the 10M50 Evaluation Kit and trying to boot from QSPI Flash using XIP (Execute In Place). I am using the Generic Serial Flash Interface (GSFI) IP, and I would also like to read and write data to the QSPI Flash after the software has started. I have the following questions: 1. Is it possible to use both XIP boot from QSPI Flash and dual configuration simultaneously? I have read the Nios® V Embedded Processor Design Handbook and believe that this should be possible from a system configuration point of view. However, I would like to confirm whether there are any limitations or considerations. 2. Regarding the GSFI HAL API support According to the Generic Serial Flash Interface Intel® FPGA IP User Guide, the GSFI HAL API supports Quartus Prime Pro Edition. Does this mean that the GSFI HAL API cannot be used with Quartus Prime Lite Edition? 3. QSPI Flash device support The 10M50 Evaluation Kit is equipped with a QSPI Flash device, the N25Q512A83GSF40F. However, this device is not listed in the section "HAL API supports the following QSPI flash device families." Does this mean that the GSFI HAL API cannot be used with this Flash device? 4. Alternative method if HAL API is not available If the GSFI HAL API cannot be used with this Flash device or with Quartus Prime Lite Edition, what is the recommended method for reading and writing data to the QSPI Flash? For example, should I directly control the GSFI registers and issue Flash commands manually, or is there another recommended software driver or method? Thank you for your support.Dual Port Nios V BSP error
I've created a Nios V qsys with dual port onchip memory in Quartus Pro 26.1 True dual port, first port connected to instruction manager, second - to data manager. Base addresses automatically assigned the same to both. But i'am unable to create the BSP due to memory regions overlapping error! Of course the addresses are same - its the same physical onchip memory! Any solytion, please? Regards, Vlad.
Mailbox Client HAL API: Erroneous behavior in flash erase boundary checks (Agilex 3 / Nios V)
Hi, I am currently working on an Agilex 3 platform using the Nios V in Quartus Prime Pro 25.3. I discovered unexpected behavior in the Mailbox Client HAL API when trying to erase 32K blocks of flash. In the file intel_mailbox_client_flash.c in function mailbox_client_flash_erase_block: The function receives a dynamic block_size as an argument but ignores it during the boundary check, relying instead on the global dev_info->region_info.block_size. Because it checks against the maximum hardware block_size (i.e., 64K) instead of the actual block_size parameter passed to the function, it mistakenly blocks legitimate erase commands at the final sectors of the region. Below is the code snippet: int mailbox_client_flash_erase_block(intel_mailbox_client* fd, int block_offset, int block_size) { if(block_offset < 0 || block_offset > dev_info->region_info.region_size - dev_info->region_info.block_size || (block_offset & (SZ_4K - 1)) != 0) { return -EINVAL; } } I suggest changing the boundary check to use the local block_size parameter that was explicitly passed to the function: if(block_offset < 0 || block_offset > dev_info->region_info.region_size - block_size || (block_offset & (SZ_4K - 1)) != 0) { return -EINVAL; } A similar logic flaw exists in the caller function mailbox_client_flash_erase. The input validation check uses the static hardware block size (dev_info->region_info.block_size) instead of taking the requested length into account. I suppose this check should prevent out-of-bounds erases in the first place, so checking if there is one 64K block left in the flash is actually pointless. int mailbox_client_flash_erase(intel_mailbox_client* fd, int offset, int length) { if(offset < 0 || offset > dev_info->region_info.region_size - dev_info->region_info.block_size) { return -EINVAL; } } I suggest using: if(offset < 0 || offset > dev_info->region_info.region_size - length) { return -EINVAL; } Any feedback on this behavior would be appreciated. Thanks!NIOS V Core Not Recognized in RiscFree IDE 25.2.1 Run Configuration
I am trying to run software that I developed using Quartus Prime Lite version 25.1 and RiscFree IDE version 25.2.1. However, in Run As > Run Configurations > Ashling RISC-V Hardware Debugging, the NIOS V core is not recognized in the Core Selection field under Target Configuration. The PIC is recognized correctly in the Device/TAP Selection field. I have found that this issue has occurred with some previous versions, but I would like to know whether this problem can also occur with RiscFree IDE version 25.2.1. If there is a known solution or workaround, I would appreciate any advice. I have attached screenshots of the issue for reference.Nios V XIP boot from UFM does not work with dual configuration on FPGA 10M50 Evaluation Kit
Hello, I am currently testing a project using Nios V on the "FPGA 10M50 Evaluation Kit". I am trying to boot the Nios V application from UFM using XIP (Execute In Place) with the dual configuration setting. However, I have not been able to successfully boot from UFM, even after checking the following items: * FPGA and board wiring * BSP Editor configuration * Standalone execution of the Nios V application (a simple LED blinking application) The Nios V application runs correctly as a standalone project, but it does not boot from UFM. I suspect that the issue may be related to my BSP Editor configuration. (I previously had some difficulties with a similar boot configuration when using Nios II.) I have attached my project files. If possible, could someone please review my project files and advise what might be causing the issue? *Note: The project was created under the D: drive on my PC.* ----------------------------------------------------------------------------------------------------------------- This is not directly related to the boot issue, but I also noticed another behavior with the Nios V application. When I tried to use "usleep()" in the application, the build completed successfully, but during execution the delay seemed to be ignored. If there is any required configuration or setting for "usleep()" to work correctly with Nios V, I would appreciate any advice. Thank you very much for your help.Introducing the Altera Community AI Responder — Beta
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