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Quartus 20.1 NIOS II ED error: Makefile:1010: recipe for target '***.elf' failed
I have just migrated from 18.1 to 20.1 Lite. I am working on a W10 machine and have installed WSL, Ubuntu, etc. NIOS II SBT is running and I was able to create a new project from template as instructed. I created a project using the "Small Hello World" template. The application and bsp projects were created. Cleaning and building the bsp project works well as does clean the application project. However, when I try to build the application project, I get the following error - 10:03:31 **** Build of configuration Nios II for project test_20_1_7 **** wsl make all wslpath: hal_bsp: No such file or directory Info: Building /mnt/c/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/ make --no-print-directory -C /mnt/c/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/ [BSP build complete] Info: Compiling hello_world_small.c to obj/default/hello_world_small.o nios2-elf-gcc.exe -xc -MP -MMD -c -IC:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/HAL/inc -IC:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp -IC:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/drivers/inc -pipe -D__hal__ -DALT_NO_C_PLUS_PLUS -DALT_NO_CLEAN_EXIT -D'exit(a)=_exit(a)' -DALT_NO_EXIT -DALT_USE_DIRECT_DRIVERS -DALT_NO_INSTRUCTION_EMULATION -DALT_USE_SMALL_DRIVERS -DSMALL_C_LIB -DALT_SINGLE_THREADED -Os -g -Wall -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global -o obj/default/hello_world_small.o hello_world_small.c Info: Linking test_20_1_7.elf nios2-elf-g++.exe -T'C:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/linker.x' -msys-crt0='C:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp/obj/HAL/src/crt0.o' -msys-lib= -LC:/a_Nightowl/wds2hdmi/rtl/qsys/software/test_20_1_7_bsp -msmallc -Wl,-Map=test_20_1_7.map -Os -g -Wall -mno-hw-div -mno-hw-mul -mno-hw-mulx -mgpopt=global -o test_20_1_7.elf obj/default/hello_world_small.o -lm -msys-lib=m nios2-elf-g++.exe: error: missing argument to '-msys-lib=' make: *** [test_20_1_7.elf] Error 1 Makefile:1010: recipe for target 'test_20_1_7.elf' failed 10:03:34 Build Finished (took 2s.438ms) I have no idea what this error means. Can any one help me?
NIOS II Simple Socket Server and 10GbE example
Hello, I would like to know if there's an example of the Simple Socket Server example project, firmware and/or gateware, to use with an 10G Ethernet core. I currently use this setup but with a 1G link (TSE core), but I want to upgrade the project to use 10G or possibly more on my Stratix V GX board. I use Quartus 18.0. Thanks in advance
Debug Know-How: Ashling* RiscFree* NIOS® V debug using Command Line
#sharing #debug #niosv Disclaimer: This article is provided as-is for educational purposes only, without warranty of any kind. Use the information at your own risk. Always verify implementations in your specific environment and consult official Altera documentation for production deployments. Introduction When a NIOS V design hangs and the RiscFree Ashling GUI becomes unresponsive, you can still debug effectively using the command line. This guide outlines clear, step-by-step instructions for setting breakpoints and monitoring system behavior using GDB server. Steps 1) Open a terminal and enter: >> niosv-shell 2) Run the following command three times to create three terminals: >> xterm& Terminal 1 is to open a port Terminal 2 is to control breakpoints Terminal 3 is to monitor output print messages 3) TERMINAL#1: Identify the JTAGIDCODE and Start GDB Server irst, display the connected JTAG device: >> jtagconfig Then start the Ashling GDB server and note down the port number (in this case is 38791): >> ash-riscv-gdb-server --auto-detect true --probe-type usb-blaster-2 --tap-number 1 --device 034BB0DD --core-number 0 4) TERMINAL#2: Load the ELF file Launch GDB: >> riscv32-unknown-elf-gdb run.elf Inside the GDB prompt: >> file run.elf >> target remote: 38791 >> load run.elf 5) TERMINAL#3: Run JUART Terminal Use JUART to monitor output: >> juart-terminal -c 1 -d 1 -i 0 This will display system logs, print messages, and output triggered by breakpoints. 6) TERMINAL#2: You may now begin debugging using standard GDB commands. Set a breakpoint: >> break <line number> Continue execution until the breakpoint: >> c Step line-by-line >> n 7) Repeat Step (6) as needed - run, monitor output via JUART, examine behavior, and continue. Tips and observations In some cases, the system hangs only when code runs continuously. This may indicate a insufficient time-to-execute issue. Running commands line-by-line (e.g., using `n`) adds implicit delay between operations, preventing hangs. If continuous execution hangs but step execution does not, consider adding delays such as: >> usleep (<value>) Start with a larger value, then gradually reduce it until the hang reappears to identify the required timing margin. For example, the following operations in the function have been identified as the root cause of insufficient time between issuing rd_word and wr_word: Use a large sleep value first to confirm that adding delay resolves the hang issue. >> #define SLEEP2 10000 If the initial delay proves effective, reduce it step‑by‑step until you find the minimum acceptable value that prevents the hang. >> #define SLEEP2 20 Conclusion This procedure should help you debug NIOS V designs reliably even when the GUI tools fail. Help the community grow—if this article was helpful, please mark it as a solution or give it a kudos so it can reach others.
Intermittent DDM Errors
Hi Everyone, Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus Prime Pro Edition software, Quartus Embedded Edition software, or select standalone tools may cause the software or tool to crash. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and 25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. For more information, see this KDB: Why do I unexpectedly observe intermittent DDM Errors? | Altera Community Sue
Arria 10 dev kit boot via epcq - software not loading
hi I'm trying to boot a Nios ii processor from EPCQ flash. I followed the steps described in the following (page 252 and on): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/nios2/edh_ed_handbook.pdf I connected the reset vector to the EPCQ controller and the exception vector to a on chip memory: when I try to convert the sof + epcq hex to jic , and use 'absolute addressing': I get: why is this the address I'm seeing? when I choose 'relative path' (and insert the appropriate address) I can convert to JIC but the software does not load from flash (HW does). I think the issue is not with the software app itself since it does work when loading from JTAG. any ideas what the issue may be? thanks!Learning Linux and choosing best Linux for Altera Arria V SoC Kit
Hello all, Thanks to Altera for providing such a great platform for learning! I am new to Linux operating system. I want to learn it and use it for Altera Arria V SoC Kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-arria-v-soc.html). Please suggest me how to start. Where can I learn basic Linux and start porting the Linux OS to Arria V SoC kit? How should I choose the best Linux OS for this kit? Thank you all in advance. Regards
Does app note AN706 apply to Arria10SoC?
Are you able to map an HPS IP Peripheral Signals to the FPGA fabric, such as a UART controller? In the case of Arria10SX Dev Kit, routing the DB9 RS232 port (of the FPGA fabric) to the HPS uart controller. (in addition to the usb-to-uart port connected to the HPS; requiring a 2nd uart) Seems I am able to choose if the signals are coming from FPGA or HPS dedicated/shared IOs in Platform designer --> HPS --> Pin Mux and Peripherals Tab. But found a similar post which is implying this is not possible for A10SoC and requires an fpga-hps bridge with corresponding IPs in the FPGA fabric. https://forums.intel.com/s/question/0D50P00003yyGafSAE/routing-hps-gpio-to-an-led-in-fpga-region?language=en_US Some clarification would be appreciated.
