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timing impact
I performed compilation on two separate servers(A and B)using identical RTL source code and identical project configurations; however, the resulting timing violations differ between the two builds, with one server A has less timing violations. Does a server with more CPU cores, higher clock speed and bigger RAM help improve project timing results?
How to generate a netlist when the design includes encrypted sources
I would like to ship my design to a customer as an encrypted netlist, however I am unable to create the netlist after a successful run, because my design includes encrypted RTL (unable to change this). I am running the following command (after running synthesis and P&R): quartus_eda my_project --simulation --format=vhdl --tool=modelsim -c my_project_revision I get the following error: Error (18580): Cannot generate netlist output files because the design includes encrypted source files: "/path/to/encrypted/rtl/file.vhdp" I see here that this was planned to be possible in "future" Quartus Prime updates, but I am using 26.1 and no such update has been made. I have also attempted to run the following command, with the exact same result: quartus_eda my_project --resynthesis --tool=modelsim Any help would be appreciated; perhaps this is plainly impossible, or perhaps there is some work-around. Thank you!
Mailbox Client IP - SEND_CERTIFICATE command through FPGA fabric
Hi colleagues, under Agilex3C (A3CY135BM16A) Non-HPS with Quartus 26.1 (latest SDM, latest IPs) how one can send compact certificates to SDM through the internal FPGA fabric? I tried it with Mailbox Client (1024/1024 FIFO depth, AXI accelerator path disabled) + SPI slave/JTAG Avalon Master, all other SDM commands (incl. the complicated ones like SPI programming with larger payloads) are working fine except this one. The error I get back all the time is 0xF00000FF (which appears as 0x3FF in SDM level1 log), so generic error, no explanation. When I load the same certificate over JTAG (external JTAG not via JTAG Avalon bridge to Mailbox Client), then it is working fine (so signature and certificate content is right). I tried both burning fuse or just loading virtual fuse with/without test bit. All gives back this same answer if it has been sent over FPGA Fabric SDM mailbox. Does anyone know any example project for this? (I tried to make it work based on ATF-A mailbox driver's VAB certificate loading command implementation (which theoretically should accept other certificates too). I believe this is something supposed to work without HPS. (otherwise you should leave JTAG enabled in your system). Links: arm-trusted-firmware/plat/altera/soc/common/include/socfpga_mailbox.h at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware arm-trusted-firmware/plat/altera/soc/common/soc/socfpga_mailbox.c at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware Thanks, PeterList of available patches for specific Quartus version
@Altera support: It is difficult and time consuming to find if there exist patch for specific issue/defect of Quartus Prime on Knowledge Base and/or Forums. It would be great to have simple page, which contain list of all publicly available patches for specific version of Quartus xx.x Lite/Standard/Pro with links to descriptions what is fixed by particular patches and download links. BR, Martin
Questa FPGA Starter Edition: Fatal WLF Error when restarting sim
Simulating some SystemVerilog code (example attached) on Questasim Starter Edition 24.1 or 25.1, when clicking on "restart" on the gui (or typing restart in the console), QuestaSim crashes and gives the following error: ** Error: Fatal WLF Error (2): allocateArchiveNumbers: unknown opcode error: 0 1 I have attached a minimal reproducible example, along with the transcript. On the example, I have found the crash only occurs when passing req_i.b to the "control_decoder" module. Passing req_i.a works fine. Defining type_t with just one member logic b also works. On the Makefile, removing -pedanticerrors also prevents the crash. Thanks
A5EG013BB18A OPN is visible in Quartus but not listed in Program File Generator
Hi everyone, I am currently working on programming an SCM FPGA board using Intel Quartus 25.1 . Our target FPGA OPN is A5EG013BB18A. I need to generate a .jic file from a .sof file by using the Program File Generator. However, when I try to select the FPGA Device in the Program File Generator, we cannot find A5EG013BB18A in the device list. The strange thing is that A5EG013BB18A can be seen in other places within Quartus, but it is not shown only in the Program File Generator device selection list. I have attached screenshots and related files showing: 1. The device can be seen in Quartus 2. The Program File Generator FPGA Device selection list 3. The content of .ini file and the .qsf file Could anyone help confirm the following? Is A5EG013BB18A supported in the Program File Generator? 2. Is there any specific .ini file setting or placement required for the Program File Generator to show this OPN? 3. Is a specific Quartus version or device package required? 4. Is there any known limitation where an OPN is visible in Quartus but not available in the Program File Generator? Any advice or reference would be appreciated. Thank you.
