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Failed to run ip-setup-simulation:
Hello Altera Community. I'm trying to simulate an example generated by the FPGA AI Suite. However I get a list of errors which is attached below in a txt file. In Settings -> IP Simulation CHECKED: Generate IP Sim model FLOW: QRUN SIMULATORS: QuestaSIM It seems like the example is already setup for simulation expect its missing a testbench. I am running Quartus in admin mode. I have installed EDA Lib. I have installed Questa. What should I do to get it working?Compile option not saved (reversed to default)
Quartus std 25.1 / Questa Altrera FPGA Ed. 64 2025.2 My project use systemverilog all designs. launch RTL Simulation/Questa from Quartus , Everytime error happen not treated as designs are systemverilog. Opening "Compile->Compile option->verilog" and chage "default" to "systemverilog" then re-load design by "do ***_run_msim_rtl_systemverilog.do" command, no error happens. But next Questa launch, same error happend and "Compile option" reversed to "default" not saved.How to fix Error(23782): Failed to find an expected report
Hey Altera Community I was messing around in the Board and IP settings trying to get simulation to work, but something went wrong and now I get this error every time I try to compile. How to fix? Info: Finished generating IP file(s) in the project. Error(23782): Failed to find an expected report while writing reporting database. Error: Quartus Prime IP Generation Tool was unsuccessful. 1 error, 6 warnings
SSLC Login Issue – "You need to enroll" loop after OTP verification
Hi, I am facing an issue with the Altera Self Service Licensing Center (SSLC). Problem: - I enrolled at licensing.altera.com successfully - I receive the OTP verification code on my email - After entering the OTP correctly, it shows: "Access to the SSLC portal requires registration Register here to get started." - This creates an infinite loop and I cannot access the portal at all I need to generate a free Questa Intel FPGA Starter Edition (SW-QUESTA) license for use with Quartus Prime Lite 24.1. Things I already tried: - Enrolled with two different email IDs - Tried Chrome, Edge, and Incognito mode - Cleared cookies and cache. Could you please either: 1. Fix my account access, OR 2. Manually generate and send the license.dat file to my email My registered email: [email protected] Thank you.
Free Licence for Max+PlusII
Hello to all, the ALTERA Support request to ask my question here in this forum, so I am here ;-) I tried to request a legacy Licence file form my old Max+PlusII (baseline 10.2) SW. I got the login, the page, but when I have to add my machine ID (which is based om the MAC address, for example) it always answers with invalid ID. How can I request a licence for this old SW (optimum an unlimited one ...) Greetings Chris OE3CPA
Connection bit order between hierarchy
Hi, I got unintended bit order of bus connection between SystemVerilog top with Block Design in lower hierarchy. I intend to connect inst3 to out[3] but Quartus connected in reversed order. Please see Technology map viewer screen shot and open archived project. Is there any Quartus option to fix this problem? This happens with (System)Verilog top only. I already experiment bdf, tdf, vhd top instead of sv, they work as expected. I am using Quartus Pro 23.2. Thanks, Masaru
quartus pro 25.3 bug?
Now I am developing a project with agilex7 base on the quartus pro 25.3. the project contains R-TILE pcie hard ip and F-tile ethernet hard ip. During board bring-up debugging, we frequently encounter non-deterministic discrepancies between actual hardware behavior and simulation results. For instance, on a certain platform, the PCIe device fails to be enumerated by the host. Probing the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. However, we have verified that no traffic is being sourced to this interface, meaning these two signals should theoretically remain idle without constant toggling. And the timing of the project is cleaning. How should we proceed to troubleshoot this issue? Should we try upgrading the Quartus version as a potential solution?flexlm error
Warning(292000): FLEXlm software error: System clock has been set back. Feature: quartus_pro License path: ... FlexNet Licensing error:-88,309. and: Error(119013): Current license file does not support the AGFD023R24C2E1VC device. Go to the Self-Service Licensing Center on the Altera website to manage your licenses (https://fpgasupport.intel.com/Licensing/license/index.html). ??? whats going on with this quartus pro 26.1 software ??? any ideas ? better to stick with vivado ?
Quartus crashes on long carry chain in Agilex 5 FPGAs
We try to manually place a carry chain in the Agilex 5 FPGAs which consists of more than 40 LABs. When we place this carry chain using set_location_assignment, Quartus crashes during the placement phase whenever the carry chain is longer than 40 LABs. Is it expected that the carry chain cannot be made longer than 40 LABs in the Agilex 5 FPGAs? Crash was observed on Quartus 25.3 and Quartus 26.1 for the devices A5ED065BB32AE4S and A5ED013BB32AE4SCS. Internal Error: Sub-system: FLABS, File: /quartus/fitter/flabs/flabs_util.cpp, Line: 96 p_to_fill->next == FLABS_OPEN
