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IEEE 1735 Encryption Public Key
We are preparing an encrypted RTL deliverable for a customer using Quartus Prime Standard Edition 21.1. Could you please confirm whether this specific edition and version supports synthesis of IEEE 1735-encrypted Verilog/SystemVerilog RTL supplied by a third-party IP vendor? If supported, could you please provide, or direct us to: The appropriate Altera/Intel public key for encrypting RTL for this tool version, together with the required key_keyowner, key_keyname, and key_method settings. The supported IEEE 1735 envelope version and encryption algorithms. Any requirements or restrictions on the encryption utility, file format, or third-party IP delivery flow. A reference encryption header or a minimal example that we can use for compatibility testing. Our current RTL encryption flow uses IEEE 1735 version 1 envelopes with vendor-specific key blocks. We would like to confirm whether adding an Altera/Intel key block is supported for the above configuration. If Quartus Prime Standard Edition 21.1 does not support this flow, could you please advise on the supported alternatives and whether a different Quartus edition or version would be required?
About Single Event Upset (SEU)
The target devices are MAX 10, Cyclone 10 LP, Cyclone V, and Agilex 3. I would like to confirm the details about SEU for these devices. Question 1: Please explain how the FIT value shown in the "Projected SEU FIT" report for a project in Quartus is calculated. We are being asked, “What is the basis and condition under which this number is derived?” Since our competitors provide this information, we would like Altera to present it as well. I have the following publicly available documents, but since they do not mention any specific calculation formulas, we are making this inquiry. https://docs.altera.com/r/docs/683869/current/an-866-mitigating-and-debugging-single-event-upsets-in-quartus-prime-standard-edition/quartus-prime-software-seu-fit-reports Question 2: Please provide information on the device structure and supporting data (numerical values) regarding SEU tolerance. Since both AMD (Xilinx) and Lattice have disclosed such information, we would like Altera to present it as well. Best Regards
Problems with registered computers in SSLC
Hello, I recently logged in to the Altera SSLC to renew a license. I used to have multiple host computers registered, which now seem to be missing: (None appear either when opening the "View All Computers" window) So I tried to re-create the computer that is to host said license, and I came upon the following error: It would seem that the computer both exists and does not exist! For the sake of seriousness and good taste, I will abstain from making any jokes about Schrödinger and quantum superposition. In any case, I see some maintenance is going on today, so that might be related to the issue. Otherwise, I would greatly appreciate if this could be looked into. Thank you and regards, NoahModelSim and Questa Starter Ed.
Hi all, The PC I currently use for FPGA development has both Quartus II 13.1 and Quartus 25.1 Std installed. Has it been verified that using Questa Starter Edition will not interfere with the existing FlexNet license environment for ModelSim? Now Questa Starter licenced by file fron SSLC, and Windows envisonment valiable SALT_LICENSE_SERVER=***_License.dat And alongside installed ModelSim use ordinary FlexNet Licencing LM_LICENSE_FILE=<<< local license servers >>>> I am asking this question because, while I was attempting to resolve the ModelSim license error mentioned below, my local administrator requested that I verify whether installing Questa Starter might affect ModelSim license management. Quatus 13.1 ModelSim license failure
Clock domain crossing?
I two vectors crossing from 150MHz-domain to 120MHz-domain, and the design assistant lists violations according to rule D101. I do not understand why only valid-bits for some of the channels get these violations. And why the data-buses seems to be fine. The vectors are actually 16 channels of data/valid busses. Every channel is prolonged to a 2x clock in the 150MHz domain, and then synchronized through dual FFs in the 120MHz domain. I have tried forcing Quartus by adding these global assignments I have also added these attributes in my source code. The technology-viewer still shows a LOGIC_CELL_COMB between *_s1[0].tvalid and *_s2[0].tvalid, shouldn't there be a direct connection between the two FFs? I am stuck understanding why this occurs, Any suggestions on what can be done?
Where to place custom .xml flash device files for Quartus Programmer?
Hello, to use flash devices that are not natively supported by Quartus programmer, a .xml device file (pgm_flash_xxxx.xml) describing the programming algorithm must be supplied along with the programming file, e.g. .jic. During code development, the .xml file is usually hold in project folder or a dedicated custom database location. But during initial device programming or reprogramming by field service, we don't have a Quartus project, just a programming file and a standalone Programmer installation, accompanied by said .xml file for non-standard devices. It would be good when .jic file location is checked for .xml file by Quartus Programmer, but that apparently isn't the case. Placing custom .xml file in programmer/xml folder (either <Quartus base directory>/devices/programmer/xml for newer Quartus Pro versions or <Quartus base directory>/quartus/common/devinfo/programmer/xml for Quartus Standard and older Quartus Pro) seems to work, is there a better option? Can we specify a custom database location for Quartus Programmer? Regards Frank
Compiling quartus design of PCIe root port example failing in WSL2
I am trying to follow the instruction for the PCIe root port example design (https://altera-fpga.github.io/rel-25.1/embedded-designs/agilex-5/e-series/premium/pcie_rp/ug-pcie_rp-agx5e-premium/). I am able to compile the design for the branch rel/26.1 in my native windows install of Quartus (version 26.1), using ```powershell git clone -b rel/26.1 https://github.com/altera-fpga/agilex5-ed-pcie-rp.git cd .\agilex5-ed-pcie-rp\src\hw\a5e065bb32aea_mdk\syn\g4x4 C:\path\to\quartus_sh --flow compile top ``` but trying the same command in WSL2 with the linux install of the same Quartus version, I get compilation errors ```bash git clone -b rel/26.1 https://github.com/altera-fpga/agilex5-ed-pcie-rp.git cd .\agilex5-ed-pcie-rp\src\hw\a5e065bb32aea_mdk\syn\g4x4 /path/to/quartus_sh --flow compile top ``` The errors I get: ``` Error (13785): VHDL Use Clause error at jtag_subsys.vhd(345): design library "hps_f2sdram" does not contain primary unit "hps_f2sdram" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 345 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(347): design library "hps_m" does not contain primary unit "hps_m" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 347 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(349): design library "jtag_subsys_address_span_extender_0" does not contain primary unit "jtag_subsys_address_span_extender_0" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 349 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(351): design library "jtag_subsys_mm_ccb_0" does not contain primary unit "jtag_subsys_mm_ccb_0" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 351 Error (13827): Ignored construct jtag_subsys_altera_mm_interconnect_1920_pikpq3i at jtag_subsys_altera_mm_interconnect_1920_pikpq3i.v(175) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/altera_mm_interconnect_1920/synth/jtag_subsys_altera_mm_interconnect_1920_pikpq3i.v Line: 175 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(357): design library "altera_mm_interconnect_1920" does not contain primary unit "jtag_subsys_altera_mm_interconnect_1920_pikpq3i" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 357 Error (13827): Ignored construct jtag_subsys_altera_mm_interconnect_1920_d6b64fi at jtag_subsys_altera_mm_interconnect_1920_d6b64fi.v(173) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/altera_mm_interconnect_1920/synth/jtag_subsys_altera_mm_interconnect_1920_d6b64fi.v Line: 173 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(359): design library "altera_mm_interconnect_1920" does not contain primary unit "jtag_subsys_altera_mm_interconnect_1920_d6b64fi" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 359 Error (13827): Ignored construct altera_reset_controller at altera_reset_controller.v(364) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji/synth/ip/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji/emif_io96b_hps_emif_io96b_hps_420_6c3i3ji_emif_0_ddr4comp/altera_reset_controller_1924/synth/altera_reset_controller.v Line: 364 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(361): design library "altera_reset_controller_1924" does not contain primary unit "altera_reset_controller" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 361 Error (13785): VHDL Use Clause error at jtag_subsys.vhd(363): design library "altera_reset_controller_1924" does not contain primary unit "altera_reset_controller" File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 363 Error (13827): Ignored construct rtl at jtag_subsys.vhd(655) due to previous errors File: /home/krar01/git-clones/agilex5-ed-pcie-rp-unmodified/src/hw/a5e065bb32aea_mdk/src/g4x4/jtag_subsys/jtag_subsys/synth/jtag_subsys.vhd Line: 655 ``` Opening the jtab_subsys.qsys file in platform designer I also get warnings about missing .ip files, among the missing ip files is the hps_f2sdram.ip file, I get a feeling that warning is related somehow. I notice that in the windows native case the generated jtag_subsys file is generated as verilog, while in WSL it is a vhdl file. I do not why the same Quartus version and build numbers would fail in WSL while it succeeds in native windows. Is there anyone who may understand what the differences might be?
