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IOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clock capable input pin on FPGA and is connected to 50MHz on board clock source. The toplevel module has iopll instantiation as following pcie_ed_iopll_0 iopll_0 ( .refclk (iopll_clk_clk), // input, width = 1, refclk.clk .locked (), // output, width = 1, locked.export .rst (resetip_ninit_done_reset), // input, width = 1, reset.reset .outclk0 (iopll_0_outclk0_clk) // output, width = 1, outclk0.clk ); "iopll_0_outclk0_clk" is supposed to be used as clock input for inner logic only. in Platform designer IOPLL is IP is configured to output only one clock at 300MHz. in the project SDC file I have following constraints #iopll Clock create_clock -period 20 [get_ports iopll_clk_clk] #derive_pll_clocks -create_base_clocks - Tried it but not supported for Agilex 10 create_generated_clock -multiply_by 6 -source [get_ports iopll_clk_clk] -name iopll_0_outclk0 [get_pins iopll_0|iopll_0_outclk0] - this is line 17 Here while compiling the design during fitter stage i see following warning messages. Warning(332174): Ignored filter at intel_rtile_pcie_ed.sdc.terp(17): iopll_0|iopll_0_outclk0 could not be matched with a pin Warning(332049): Ignored create_generated_clock at intel_rtile_pcie_ed.sdc.terp(17): Argument <targets> with value [get_pins {iopll_0|iopll_0_outclk0}] contains zero elements This tells me that the IOPLL clocks are not constrained properly and Quartus wont be able to evaluate clock paths correctly for internally generated 300MHz clock. can you help me in figuring out what am i doing wrong here? How can I correctly constraint that iopll is fed with 50MHz clock and its output is 300MHz clock?[Agilex 7F] How to setup my EMIF IPs for the toolkit?
Hi, I've been trying to reconfigure my existing EMIF IPs to make them reachable from the EMIF toolkit and be able to generate some eye diagrams. The topology I have : 2x EMIF calib IPs 7x EMIF IPs One calib IP is connected to 3 EMIFs and the other to the 4 remaining. For the calib IPs, I selected "Add EMIF Debug Interface". For the EMIFs I did not do anything since "Note: Calibration Debug Options are set from EMIF Calibration IP which applies to all EMIFs connected to an I/O row". When opening the system console, I can see the instances in the System Explorer tab, but not in the Toolkit Explorer (I loaded the sof file). Am I doing something wrong? Note that I DO NOT want to start again from an example design, or let me know if it won't change anything for me in terms of settings, behavior, ... Also, if there's a way to generate the eye diagram "by hand" from the exported cal_debug port, I am more than interested. If there's any other way to automate the process of generating the eye diagrams, I would also be interested! Thanks!
Unable to Enrol into SSLC Due to Microsoft Authentication App Issue
Hello, I’m experiencing issues signing in to my Intel account to access my licenses. The login process requires the Microsoft Authentication App, but when I open the app, it displays “Action Required” and does not allow me to proceed. On the Intel website, the only available sign-in options are: Entering a code generated by the Microsoft Authenticator app Approving the sign-in request through the Microsoft Authenticator app Both options rely on the app, which is currently not working for me. As a result, I cannot sign in to my account. Could you please advise on how to resolve this issue or provide an alternative way to access my account? Thank you for your assistance.
Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, Alkesh
NIOS V Sysnthesis Fails with Quartus 25.1 Lite
Hi, I used Quartus 23.1 Lite for a couple of months and have now switched to Quartus 25.1 Lite. Since the version update my NIOS V Plattform Designer Projects do not synthesize any longer. Synthesis fails with: Info (12128): Elaborating entity "niosv" for hierarchy "niosv:u0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0_hart" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (12152): Can't elaborate user hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Info (144001): Generated suppressed messages file /home/simon/Documents/QuartusPrime/MAX10_InternalFlash_Ticket/output_files/MAX10_InternalFlash_Ticket.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 30 warnings Error: Peak virtual memory: 369 megabytes Error: Processing ended: Mon Nov 10 09:24:51 2025 Error: Elapsed time: 00:00:39 Error: Total CPU time (on all processors): 00:01:41 Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 30 warnings I am using the DE10-Lite Board with the Golden Top example Design and add a very basic Nios V to it. //======================================================= // Structural coding //======================================================= niosv u0 ( .clk_clk (MAX10_CLK1_50), // clk.clk .reset_reset_n (1'b1) // reset.reset_n ); Any idead how I can fix that Issue? Best regards SimonAgilex 5 IOPLL Max Numbers and Tool Display Mismatch
Hello everyone Let me discuss the title. [Question] What is the maximum number of IOPLLs (Bank IOPLLs, Fabric Feeding IOPLLs, and perspective of whether System PLL can be used for other purpose ) on an A5EC008BB32AE5S, both device wide and bank/block wise? In particular, I would like to know the official opinion on how Quartus Pro Edition (Fitter/Report) and Power and Thermal Calculator count the upper limit on IO96B (HSIO) banks and the upper limit on HVIO blocks. Please check the attached file for details. Best RegardsRealistic values for set_max_skew
I have a design with asynchronous input and output bus signals. For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I also do not care how much time it takes from the last register to the output ports. The only thing that I really care about is, the skew of the bus signals. I have created a very simple dummy design and added sdc design constraints. module top( input clk, input [1:0] input_bus, output reg [1:0] output_bus ); reg [1:0] register; always @(posedge clk) begin register <= input_bus; output_bus <= register; end endmodule create_clock -name clk -period 20 [get_ports clk] set_max_skew -from [get_ports {input_bus[*]}] 0.5 set_max_skew -to [get_ports {output_bus[*]}] 0.5 Timing Analyzer fails. I do not have a lot of experience with SDC constraints and bus timing. My feelfing is, that 0.5ns bus skew is not unrealistic. Is my expectation wrong, or am I doing something wrong?