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Quartus Prime Pro Hierarchy View has blank rows for some instances
Hello, I am using Quartus Prime Pro and after a compilation of my design, the Hierarchy view in the Project Navigator shows the board utilization metrics such as ALMs needed, DSP blocks, etc. I have noticed that some lines appear completely blank. I didn't initially believe these are due to components being synthesized out because these components that appear blank appear in the RTL viewer and my understanding was that the RTL Viewer wouldn't show the component if it was synthesized out. I am looking to confirm why some instances appear as blank items in the Hierarchy view. Is the tool taking advantage of resource sharing and therefore no new resources are used for that instance? Does the tool refrain from repeating data so that's why I have 1 instance with data and 2 others that are the same component without data? Is a blank cell and a 0 the same thing expressed differently depending on if the row as a whole was 0s? Is this just due to the tool not wanting to repeat itself because I've noticed I can get utilization metrics for instance_0 of a component but instance_1 and _2 of the same component are blank. Any subcomponents of a blank instance are also always blank as well. Normally there aren't many blank lines and the components were small enough for me to assume it was resource sharing, but with my current design, the components that are blank are seemingly pretty large and complicated so I'd like to learn more about how the tool is reporting and I haven't found an answer in your published documentation yet.
Realistic values for set_max_skew
I have a design with asynchronous input and output bus signals. For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I also do not care how much time it takes from the last register to the output ports. The only thing that I really care about is, the skew of the bus signals. I have created a very simple dummy design and added sdc design constraints. module top( input clk, input [1:0] input_bus, output reg [1:0] output_bus ); reg [1:0] register; always @(posedge clk) begin register <= input_bus; output_bus <= register; end endmodule create_clock -name clk -period 20 [get_ports clk] set_max_skew -from [get_ports {input_bus[*]}] 0.5 set_max_skew -to [get_ports {output_bus[*]}] 0.5 Timing Analyzer fails. I do not have a lot of experience with SDC constraints and bus timing. My feelfing is, that 0.5ns bus skew is not unrealistic. Is my expectation wrong, or am I doing something wrong?
JTAG timing violations
Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC "Agilex 7" in SDC file - I have create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group {altera_reserved_tck} I am getting timing violation in JTAG path (n/a domain). Lets ignore IOPLL domain violations for this thread. Attached is the timing compilation results for "n/a" path. I need your help in resolving JTAG timing violations. I tried to refer earlier threads on the "JTAG violations" but its not quite helping so opening this thread. thanks
Agilex 5 IOPLL Max Numbers and Tool Display Mismatch
Hello everyone Let me discuss the title. [Question] What is the maximum number of IOPLLs (Bank IOPLLs, Fabric Feeding IOPLLs, and perspective of whether System PLL can be used for other purpose ) on an A5EC008BB32AE5S, both device wide and bank/block wise? In particular, I would like to know the official opinion on how Quartus Pro Edition (Fitter/Report) and Power and Thermal Calculator count the upper limit on IO96B (HSIO) banks and the upper limit on HVIO blocks. Please check the attached file for details. Best RegardsUnable to Access Quartus Prime Licenses
We have atleast two Quartus Prime licenses that we have not been able to access for a while and due to an email domain change we were unable to login via SSO. After contacting Intel Support we finally managed to login to the portal but now see that no licenses are available to us and no way of seeing previous statuses. Intel Support told us to use this forum as they are unable to assist.[Agilex 7F] How to setup my EMIF IPs for the toolkit?
Hi, I've been trying to reconfigure my existing EMIF IPs to make them reachable from the EMIF toolkit and be able to generate some eye diagrams. The topology I have : 2x EMIF calib IPs 7x EMIF IPs One calib IP is connected to 3 EMIFs and the other to the 4 remaining. For the calib IPs, I selected "Add EMIF Debug Interface". For the EMIFs I did not do anything since "Note: Calibration Debug Options are set from EMIF Calibration IP which applies to all EMIFs connected to an I/O row". When opening the system console, I can see the instances in the System Explorer tab, but not in the Toolkit Explorer (I loaded the sof file). Am I doing something wrong? Note that I DO NOT want to start again from an example design, or let me know if it won't change anything for me in terms of settings, behavior, ... Also, if there's a way to generate the eye diagram "by hand" from the exported cal_debug port, I am more than interested. If there's any other way to automate the process of generating the eye diagrams, I would also be interested! Thanks!
Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
