Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?Duplicate_hierarchy_depth / duplicate_register
According to timing recommendations I am trying to manually duplicate logic using either set_instance_assignment -name duplicate_hierarchy_depth reg level or set_instance_assignment -name duplicate_register reg level according to AN-1016 section 4.2.4.2. But, Quartus Prime 25.1 Lite complains that duplicate_hierarchy_depth is an illegal assignment. duplicate_register seems to be ignored by Quartus and I cannot find either of them in the Assignment Editor. Any suggestions to what I am doing wrong?
how to reduce clock skew between synchronous clock
I am working on Agilex 7 FPGA with quartus 25.3 software. In my project, there is 2 synchronous clocks that fast_clock is 416M and slow_clock is 208M. the clock scheme is ref_clk_100m -> IOPLL -> 416M -> clk_ctrl_div_ip -> 416M/208M. And there is data transfer between clk_fast and clk_slow. after compiling the whole design, I found there is large timing violation in the path that from clk_fast to clk_slow by timing report. from the clk_fast-clk_slow timing path, the clock skew has -700ps from clk_fast-clk_fast or clk_slow-clk_slow timing path, the clock skew is -5ps that is expected. so how to reduce clock skew between synchronous clock? and could you provide more suggestions about how to implement data transfer clk_2x to clk_1x?
Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, Alkesh
IOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clock capable input pin on FPGA and is connected to 50MHz on board clock source. The toplevel module has iopll instantiation as following pcie_ed_iopll_0 iopll_0 ( .refclk (iopll_clk_clk), // input, width = 1, refclk.clk .locked (), // output, width = 1, locked.export .rst (resetip_ninit_done_reset), // input, width = 1, reset.reset .outclk0 (iopll_0_outclk0_clk) // output, width = 1, outclk0.clk ); "iopll_0_outclk0_clk" is supposed to be used as clock input for inner logic only. in Platform designer IOPLL is IP is configured to output only one clock at 300MHz. in the project SDC file I have following constraints #iopll Clock create_clock -period 20 [get_ports iopll_clk_clk] #derive_pll_clocks -create_base_clocks - Tried it but not supported for Agilex 10 create_generated_clock -multiply_by 6 -source [get_ports iopll_clk_clk] -name iopll_0_outclk0 [get_pins iopll_0|iopll_0_outclk0] - this is line 17 Here while compiling the design during fitter stage i see following warning messages. Warning(332174): Ignored filter at intel_rtile_pcie_ed.sdc.terp(17): iopll_0|iopll_0_outclk0 could not be matched with a pin Warning(332049): Ignored create_generated_clock at intel_rtile_pcie_ed.sdc.terp(17): Argument <targets> with value [get_pins {iopll_0|iopll_0_outclk0}] contains zero elements This tells me that the IOPLL clocks are not constrained properly and Quartus wont be able to evaluate clock paths correctly for internally generated 300MHz clock. can you help me in figuring out what am i doing wrong here? How can I correctly constraint that iopll is fed with 50MHz clock and its output is 300MHz clock?
Realistic values for set_max_skew
I have a design with asynchronous input and output bus signals. For the input bus signals I do not care how much time it takes from the Input Ports to the first register. For the output signals I also do not care how much time it takes from the last register to the output ports. The only thing that I really care about is, the skew of the bus signals. I have created a very simple dummy design and added sdc design constraints. module top( input clk, input [1:0] input_bus, output reg [1:0] output_bus ); reg [1:0] register; always @(posedge clk) begin register <= input_bus; output_bus <= register; end endmodule create_clock -name clk -period 20 [get_ports clk] set_max_skew -from [get_ports {input_bus[*]}] 0.5 set_max_skew -to [get_ports {output_bus[*]}] 0.5 Timing Analyzer fails. I do not have a lot of experience with SDC constraints and bus timing. My feelfing is, that 0.5ns bus skew is not unrealistic. Is my expectation wrong, or am I doing something wrong?JTAG timing violations
Hello Following are my project details LAST_QUARTUS_VERSION "25.1.0 Pro Edition" DEVICE AGIB027R29A1E2VC "Agilex 7" in SDC file - I have create_clock -name {altera_reserved_tck} -period 30 [get_ports {altera_reserved_tck}] set_clock_groups -asynchronous -group {altera_reserved_tck} I am getting timing violation in JTAG path (n/a domain). Lets ignore IOPLL domain violations for this thread. Attached is the timing compilation results for "n/a" path. I need your help in resolving JTAG timing violations. I tried to refer earlier threads on the "JTAG violations" but its not quite helping so opening this thread. thanks
