Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?
timing violation fix
hi, I am working on the project that base on agilex 7 fpga. project background: the compile setting is superior performance, sys clock is 416Mhz the ALM resources of the project has occupied the 70%, and has WNS -0.9 ns, TNS -29ooo ns violation. do you have better metholodgies for timing fix？ now my work flow: first analyze the fit.retiming.rpt and fit.fastforward.rpt, add pipe or register according to critical chain reported in the retiming.rpt, then start to next compile I doesn't analyze the fit.timing.rpt, because the endpoint is too large, and the work efficiency is lowrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top. background: clk freq is 416Mhz; all design use asynchronous reset; after fitting all design, the timing report about recovery violation has -1.8ns. for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network? figure 1: for compasion，I have taken the follwoing screenshot of the common path routing as figure 2 here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns. figure 2:
CYCLONE IVE ODDR delay mismatch
Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec. I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses. I'm attaching the project, hoping some experts can help me. The ddr registers are correctly instantiated, but in the timing analysis, the bit(3) coming out of the fpga is delayed compared to all the others: TIMING ON BUS_A: TIMING ON BUS_B: REGULAR DELAY: BIG DELAY: The only difference I see is that the "slow" pins are both also Vrefs (pin 105 and pin 80): Could this be the reason? regards, LUCA.how to reduce clock skew between synchronous clock
I am working on Agilex 7 FPGA with quartus 25.3 software. In my project, there is 2 synchronous clocks that fast_clock is 416M and slow_clock is 208M. the clock scheme is ref_clk_100m -> IOPLL -> 416M -> clk_ctrl_div_ip -> 416M/208M. And there is data transfer between clk_fast and clk_slow. after compiling the whole design, I found there is large timing violation in the path that from clk_fast to clk_slow by timing report. from the clk_fast-clk_slow timing path, the clock skew has -700ps from clk_fast-clk_fast or clk_slow-clk_slow timing path, the clock skew is -5ps that is expected. so how to reduce clock skew between synchronous clock? and could you provide more suggestions about how to implement data transfer clk_2x to clk_1x?
Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, Alkesh
