retiming issue
we develop a project with agilex7 fpga and using quartus pro 25.3 version. now we fix timing by analyze the retiming report. we see the following retiming restriction: But the register GEN_REG_INUT.R_DATA[0][0] is directly driven by quartus hyper register, and it has no power up value and no sync reset. the retiming critical path as follow: -------------------------------------------+ ; Critical Chain Details ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Path Info ; Register ; Register ID ; Element ; +--------------------------+-------------------------+-------------+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ ; Power-up Restriction ; ALM Register ; #1 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]|q ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X221_Y195_N0_I99 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~R1_X221_Y195_N0_I10 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~C4_X220_Y191_N0_I11 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LOCAL_INTERCONNECT_X220_Y191_N0_I26 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~BLOCK_INPUT_MUX_PASSTHROUGH_X220_Y191_N0_I35 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~LAB_RE_X220_Y191_N0_I39 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|dataf ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn|combout ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~cw_la_lab/lab_lut6outt[4] ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X220_Y191_N0_I138 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X220_Y190_N0_I17 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X220_Y190_N0_I16 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X208_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X196_Y190_N0_I2 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y182_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X195_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X184_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X172_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X160_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X148_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X136_Y174_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y166_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y158_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y150_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y142_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X135_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R12_X124_Y134_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y126_N0_I0 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C8_X123_Y118_N0_I0 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R0_X123_Y118_N0_I2 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R2_X124_Y118_N0_I15 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_R1_X126_Y118_N0_I31 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y118_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_C1_X126_Y119_N0_I30 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LOCAL_INTERCONNECT_X126_Y120_N0_I61 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_BLOCK_INPUT_MUX_PASSTHROUGH_X126_Y120_N0_I80 ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg_rst_f|GEN_REG_INPUT.R_data[0][0]~xsyn~_LAB_RE_X126_Y120_N0_I82 ; ; Long Path (Critical) ; Bypassed Hyper-Register ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|pack_data_padding_cross~xtophalf/xale2/xcw_ml_le_regctrl/xcw_la_le_regctrl_reg/sclr_out ; ; Long Path (Critical) ; ; ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4]|sclr ; Long Path (Critical) ; ALM Register ; #2 ; x_blk_pe|x_pe|x_pe_top_no_hmc|x_pe_pkg|x_pe_pkg_pkt_pack|x_pack_data_shifter|bcnt[4] ; why quartus report the retiming restriction?fanout issue
now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the most of number of duplicates is 4, how can we improve the number of duplicates to further to reduce fanout and congestion? quartus provides the GLOBAL_SIGNAL_PROMOTION_FANOUT_THRESHOLD setting, which the default is 50. In my project many signal fanout exceed 50, but I doesn't think the signals are being routed global network. so for non-global high fanout signals, what should I do？manually duplicating many high-fanout nets in the RTL is not practical.
Timing analysis - long combinational path
Hi, Running Timing Analyzer I get violations due to long combinational paths. Looking at the path in the technology map viewer, it looks like this leftmost block = registerbank holding a configurable value used by the other two modules center/rightmost block = two identical modules using the register-value I can see the long path, but I do not understand why it is implemented like this. Why is the register-value routed through dec_filter:15 to dec_filter:9, and not getting the value directly from the register-bank-module to the left? Is there anything I can do to force a different implementation?timing violation fix
hi, I am working on the project that base on agilex 7 fpga. project background: the compile setting is superior performance, sys clock is 416Mhz the ALM resources of the project has occupied the 70%, and has WNS -0.9 ns, TNS -29ooo ns violation. do you have better metholodgies for timing fix？ now my work flow: first analyze the fit.retiming.rpt and fit.fastforward.rpt, add pipe or register according to critical chain reported in the retiming.rpt, then start to next compile I doesn't analyze the fit.timing.rpt, because the endpoint is too large, and the work efficiency is lowrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top. background: clk freq is 416Mhz; all design use asynchronous reset; after fitting all design, the timing report about recovery violation has -1.8ns. for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network? figure 1: for compasion，I have taken the follwoing screenshot of the common path routing as figure 2 here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns. figure 2:
CYCLONE IVE ODDR delay mismatch
Hello Altera Experts! I am using Quartus Standard 24.1.. I'm building a 10-bit parallel output interface to drive a DAC. I'm using the oddr (ALTDDIO_OUT) registers so that all bits output simultaneously. 9 of the 10 bits are aligned, while one has an additional delay of about 2 nsec. I created two 10-bit buses (to drive two DACs), and the strange thing is that bit (3) is always delayed on both buses. I'm attaching the project, hoping some experts can help me. The ddr registers are correctly instantiated, but in the timing analysis, the bit(3) coming out of the fpga is delayed compared to all the others: TIMING ON BUS_A: TIMING ON BUS_B: REGULAR DELAY: BIG DELAY: The only difference I see is that the "slow" pins are both also Vrefs (pin 105 and pin 80): Could this be the reason? regards, LUCA.
