fanout issue

Question

now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation.

from the fitter duplication summary report below, we can see that the most of number of duplicates is 4, how can we improve the number of duplicates to further to reduce fanout and congestion?
quartus provides the GLOBAL_SIGNAL_PROMOTION_FANOUT_THRESHOLD setting, which the default is 50. In my project many signal fanout exceed 50, but I doesn't think the signals are being routed global network. so for non-global high fanout signals, what should I do？manually duplicating many high-fanout nets in the RTL is not practical.

sstrell · Answer

Can you show the actual failing paths in the timing report (a detailed slack/path report to see all the delay elements along the path)?&nbsp; Have you looked at the failing paths in the Chip Planner to see if there might be physical factors involved with the placement of the failing paths?

zjj · Answer

the fit summary report isthere is 48809 failing end points, I give the one path:&nbsp;

richardt_altera · Answer

You might need to manually duplicate the register to reduce the fan-out. Currently we don't have a global assignment that can set the max fan-out for all non-global signals.
Checkout the user guide below:
https://docs.altera.com/r/docs/683641/25.3.1/quartus-prime-pro-edition-user-guide-design-optimization/duplicate-registers-for-fan-out-control

Regards,
Richard Tan

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fanout issue

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