Forum Discussion
zjj
Occasional Contributor
Occasional Contributorfanout issue
now I develop a project with agilext7 FPGA, the sysclk is 416MHz. the project has still WNS=-500ps TNS=-5000ns violation. from the fitter duplication summary report below, we can see that the mos...
sstrell
Super Contributor
Super ContributorCan you show the actual failing paths in the timing report (a detailed slack/path report to see all the delay elements along the path)? Have you looked at the failing paths in the Chip Planner to see if there might be physical factors involved with the placement of the failing paths?
zjjthe fit summary report is
there is 48809 failing end points, I give the one path:
