Quartus Prim Pro: "Fatal Error: Segment Violation, Access Violation"
Hi, I am working with Quartus Prime Pro 24.1. Unfortunately, I have encountered several issues when compiling my project on different machines and operating systems. While the project compiles and builds the bitstream without any problems on Windows Server 10, I receive a fatal error on Windows 11 and Ubuntu 24 for the same design, at the "support-logic Generation" phase. All machines are relatively powerful and equipped with more than 32 GB of RAM. I have also disabled parallel compilation, but the error still occurs. Additionally, I tested Quartus 24.3.1 and observed the same behavior. Error on Ubuntu24 machine: Error on Win11 machine: Does it have to do with our JESD float license or the JESD IP itself? I'm asking because it seems that we have this issue only with projects that include Altera JESD IP. I would appreciate it if you could help me resolve this issue. Best, SAH
Compilation error due to LPDDR5 I/O standard setting
I don't use Altera LPDDR5 IP in Agilex 5 E-series device, just write a Multi-Purpose Command to access the LPDDR5 device. And in the Quartus Pin planner, set the related pins for 0.7V LVSTL and DIFFERENTIAL 0.7-V LVSTL, I found that it would cause the fitter error. It seems that 0.7V LVSTL and DIFFERENTIAL 0.7-V LVSTL only can support Altera LPDDR5 IP usage. Error message as below, Error(24116): I/O standard option is set to Differential 0.7-V LVSTL for pin lp5a_ck_t~output but the GPIO usage mode does not support the setting. But if I try to modify I/O standard to 1.05V LVSTL and DIFFERENTIAL 1.05-V LVSTL for all related pins, and it can get the compilation pass. Could you help to provide workaround for this issue?
How can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?
I am an engineer in Terasic, I am writting a tutorial for Agilex 5. I use Quartus Pro 25.1, there is a sopc-create-header-files in \quartus\sopc_builder\bin path, I want to generate a header file in Windows system.however, I couldn't use it in Win10 system. I tried it in Nios V command Shell: even I used Windows WSL: or in Windows PowerShell： Thanks for your advice. Doreen
Intermittent DDM Errors
Hi Everyone, Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus Prime Pro Edition software, Quartus Embedded Edition software, or select standalone tools may cause the software or tool to crash. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and 25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. For more information, see this KDB: Why do I unexpectedly observe intermittent DDM Errors? | Altera Community Sue
Agilex 5 – Critical HSSI Error in JESD204B Example Design
Hi, I am bringing up the JESD204B interface on the dev kit. For this, I used the "Generate Example Design" option with the following parameters: When I generate the project and start synthesis, it reaches the "HSSI Support Logic Generation" stage, and Quartus reports the following critical error: It turns out that the generated file contains an inconsistency in the generated HSSI metadata. My fix was to replace the entry in: The problem is that after updating the Qsys file, it gets changed back to intel_jesd_RX, and HSSI reports the critical error again. If there is already a fix or workaround for this issue, please let me know. For now, I added a simple script that I run from PowerShell: that replaces this value with the correct one:
Quartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, MichaelAutomatically added negative node for TDS output doesn't work with Agilex 5
Hello, I'm trying to build a basic SE to DE converter on Agilex 5 module SEtoDE ( input SE, output DE ); assign DE = SE; endmodule I assign respective IO standards and use locations chosen by Quartus Resulting in this .qsf assignments set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE Compilation on Quartus 25.3.1 however doesn't produce a programming file due to below listed warnings Critical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details. Critical Warning(15714): Some pins are missing I/O Standard assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------------------------------------------------------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; +----------+-----------------------------------------------------------------------------------------------+ There are essentially two kinds of warnings, both unexpected and only occuring with Agilex 5 (and also Agilex 3). With Agilex 7 or Cyclone 10 GX, the design compiles flawlessly. 1. Warnings for negative pin: Missing I/O standard etc. 2. Missing termination setting It turns out, that the problem can be fixed by adding an explicit I/O standard for the negative pin, although it shouldn't be required according to Quartus User Manual. Then the warning level reduces and programming files are generated Warning(25315): Some pins are missing drive strength (current strength) and/or slew rate assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Missing termination setting ; +----------+-----------------------------+ To remove this warning, we also need to assign dummy termination settings to the TDS outputs set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to DE -entity SEtoDE Presume this should never happen Regards FrankQuartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.error in JTAG server (error code 35) and autodetect (unable to scan device chain) Quartus 18.1
Hello fellow members, I have a Max10 FPGA Evaluation Kit board (10M08SAE144C8G) which i want to flash via JTAG. For this, i have installed Quartus Prime (18.1 version) and have USB Blaster 2 as an interface. After connecting the hardware, the LEDs on the board are stable. When i execute autodetect on the programmer , i get a dialog box stating "unable to scan device chain . Hardware is not connected"(screenshot attached). In the hardware setup , i coulkd see the usb blaster variant is added but still this error occurs. Similary when i try to run the .pof file , the diagnosis show "unexpected error in JTAG server -- error code 35" (screenshot attached). I checked the driver and it seems the USB blaster driver is also updated. On the command prompt, it shows 1) USB-Blaster variant [USB-1] Unable to lock chain - Hardware not attached Has someone encountered this issue before. Any help or suggestion would be highly appreciated. The screenshots can be seen in the attachments. Thanks. Best Regards, Ali
