Hard Reset Required After Each Boundary Scan Operation
Hello there, I am working on a project involving JTAG operations (specifically boundary scan on the data register) using Quartus Prime Standard (v24) and a USB-Blaster cable. Issue: After every scan operation, I need to perform a hard reset on the device connected to the cable. If I skip the hard reset, the next scan returns incorrect TDO values. I have tried performing a soft reset after each operation, but this does not resolve the issue. Only a hard reset consistently allows me to get the correct TDO results. Sequence being used (via my Python library executing TCL commands): open_device -hardware_name {USB-Blaster [USB-0]} -device_name {@1: JTAG_DEVICE (0x12345678)} device_lock -timeout 10000 device_ir_shift -ir_value 0x00000000 puts "TDO is: 0x[device_dr_shift -length 48 -value_in_hex]" device_unlock close_device Notes: - The Python library manages TCL sessions in a dedicated terminal. - I observe the same issue when performing these operations using Quartus directly. My question: Is there a Quartus or TCL command or procedure that can help avoid the need for a hard reset after each boundary scan operation? Or is there a way to reliably ensure the correct TDO value is returned every time without hard resetting the device? Thank you for your assistance.
Quartus Pro 25.3 crash using rhel7/8
Hello everybody I'm working on an Agilex-5 project since fex months on our internal couputer farm using Quartus Pro 25.3. To generate the final bitstream, a bash script is used to execute all the steps. Until now, we have no specific issue using this script with Quartus. But since few days, we're unable to generate the project because Quartus Pro returns strange errors (see attachments). We also tried to use latest 23.5.1 version on an Ubuntu host under WSL and we also saw the same errors. Running Quartus GUI may also end with same error. (see quartus_4.png) Has anyone already experienced this issue? Thanks a lot Benjamin
Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, Alkesh
Trying to print warning messages from tcl build script
I am using quartus prime v22.1 std lite and have a build script for a max10 FPGA. It seems to build correctly, but i want to create a log file containing any errors/warnings etc. Every time the tcl fails at the 'get_messages' command (and also 'get_message_count' command), how can I generate the log file from within the tcl script? Thanks Section of script file shown below: # set compilation output folder to "factory" and compile project_open -revision wrapper factory-524-069 set_global_assignment -name PROJECT_OUTPUT_DIRECTORY "./factory" # open log file for writing set log_file "quartus_warnings.log" set fp [open $log_file w] fconfigure $fp -encoding utf-8 execute_flow -compile # filter warnings # Quartus stores messages in the internal database; we can query them load_package report load_report set msgs [get_messages -type warning] # Write warnings to log file foreach msg $msgs { puts $fp $msg } project_close # close log file close $fp the load_package report and load report seem to have no effect but were included in one example script I found.
Quartus Prime Pro Hierarchy View has blank rows for some instances
Hello, I am using Quartus Prime Pro and after a compilation of my design, the Hierarchy view in the Project Navigator shows the board utilization metrics such as ALMs needed, DSP blocks, etc. I have noticed that some lines appear completely blank. I didn't initially believe these are due to components being synthesized out because these components that appear blank appear in the RTL viewer and my understanding was that the RTL Viewer wouldn't show the component if it was synthesized out. I am looking to confirm why some instances appear as blank items in the Hierarchy view. Is the tool taking advantage of resource sharing and therefore no new resources are used for that instance? Does the tool refrain from repeating data so that's why I have 1 instance with data and 2 others that are the same component without data? Is a blank cell and a 0 the same thing expressed differently depending on if the row as a whole was 0s? Is this just due to the tool not wanting to repeat itself because I've noticed I can get utilization metrics for instance_0 of a component but instance_1 and _2 of the same component are blank. Any subcomponents of a blank instance are also always blank as well. Normally there aren't many blank lines and the components were small enough for me to assume it was resource sharing, but with my current design, the components that are blank are seemingly pretty large and complicated so I'd like to learn more about how the tool is reporting and I haven't found an answer in your published documentation yet.
NIOS V Sysnthesis Fails with Quartus 25.1 Lite
Hi, I used Quartus 23.1 Lite for a couple of months and have now switched to Quartus 25.1 Lite. Since the version update my NIOS V Plattform Designer Projects do not synthesize any longer. Synthesis fails with: Info (12128): Elaborating entity "niosv" for hierarchy "niosv:u0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0_hart" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (12152): Can't elaborate user hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Info (144001): Generated suppressed messages file /home/simon/Documents/QuartusPrime/MAX10_InternalFlash_Ticket/output_files/MAX10_InternalFlash_Ticket.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 30 warnings Error: Peak virtual memory: 369 megabytes Error: Processing ended: Mon Nov 10 09:24:51 2025 Error: Elapsed time: 00:00:39 Error: Total CPU time (on all processors): 00:01:41 Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 30 warnings I am using the DE10-Lite Board with the Golden Top example Design and add a very basic Nios V to it. //======================================================= // Structural coding //======================================================= niosv u0 ( .clk_clk (MAX10_CLK1_50), // clk.clk .reset_reset_n (1'b1) // reset.reset_n ); Any idead how I can fix that Issue? Best regards SimonState machine question in Arria X device
Hello all, In my design, there has a state machine having 28 states. The function is all good in RTL simulation. After full compilation and program to the device. There will be some state doesn't work. Checking the state machine viewer, the state machine using one-hot encoding style. If I only change encoding style to "gray" or "sequential", RTL code doesn't change. The state machine work correctly! What's the problem? How can I debug and prevent this problem? Environment : Quartus Prime Pro Edition 19.2. Thank you all.
Agilex 5 IOPLL Max Numbers and Tool Display Mismatch
Hello everyone Let me discuss the title. [Question] What is the maximum number of IOPLLs (Bank IOPLLs, Fabric Feeding IOPLLs, and perspective of whether System PLL can be used for other purpose ) on an A5EC008BB32AE5S, both device wide and bank/block wise? In particular, I would like to know the official opinion on how Quartus Pro Edition (Fitter/Report) and Power and Thermal Calculator count the upper limit on IO96B (HSIO) banks and the upper limit on HVIO blocks. Please check the attached file for details. Best Regards
IOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clock capable input pin on FPGA and is connected to 50MHz on board clock source. The toplevel module has iopll instantiation as following pcie_ed_iopll_0 iopll_0 ( .refclk (iopll_clk_clk), // input, width = 1, refclk.clk .locked (), // output, width = 1, locked.export .rst (resetip_ninit_done_reset), // input, width = 1, reset.reset .outclk0 (iopll_0_outclk0_clk) // output, width = 1, outclk0.clk ); "iopll_0_outclk0_clk" is supposed to be used as clock input for inner logic only. in Platform designer IOPLL is IP is configured to output only one clock at 300MHz. in the project SDC file I have following constraints #iopll Clock create_clock -period 20 [get_ports iopll_clk_clk] #derive_pll_clocks -create_base_clocks - Tried it but not supported for Agilex 10 create_generated_clock -multiply_by 6 -source [get_ports iopll_clk_clk] -name iopll_0_outclk0 [get_pins iopll_0|iopll_0_outclk0] - this is line 17 Here while compiling the design during fitter stage i see following warning messages. Warning(332174): Ignored filter at intel_rtile_pcie_ed.sdc.terp(17): iopll_0|iopll_0_outclk0 could not be matched with a pin Warning(332049): Ignored create_generated_clock at intel_rtile_pcie_ed.sdc.terp(17): Argument <targets> with value [get_pins {iopll_0|iopll_0_outclk0}] contains zero elements This tells me that the IOPLL clocks are not constrained properly and Quartus wont be able to evaluate clock paths correctly for internally generated 300MHz clock. can you help me in figuring out what am i doing wrong here? How can I correctly constraint that iopll is fed with 50MHz clock and its output is 300MHz clock?
