Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.
Hard Reset Required After Each Boundary Scan Operation
Hello there, I am working on a project involving JTAG operations (specifically boundary scan on the data register) using Quartus Prime Standard (v24) and a USB-Blaster cable. Issue: After every scan operation, I need to perform a hard reset on the device connected to the cable. If I skip the hard reset, the next scan returns incorrect TDO values. I have tried performing a soft reset after each operation, but this does not resolve the issue. Only a hard reset consistently allows me to get the correct TDO results. Sequence being used (via my Python library executing TCL commands): open_device -hardware_name {USB-Blaster [USB-0]} -device_name {@1: JTAG_DEVICE (0x12345678)} device_lock -timeout 10000 device_ir_shift -ir_value 0x00000000 puts "TDO is: 0x[device_dr_shift -length 48 -value_in_hex]" device_unlock close_device Notes: - The Python library manages TCL sessions in a dedicated terminal. - I observe the same issue when performing these operations using Quartus directly. My question: Is there a Quartus or TCL command or procedure that can help avoid the need for a hard reset after each boundary scan operation? Or is there a way to reliably ensure the correct TDO value is returned every time without hard resetting the device? Thank you for your assistance.Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, AlkeshState machine question in Arria X device
Hello all, In my design, there has a state machine having 28 states. The function is all good in RTL simulation. After full compilation and program to the device. There will be some state doesn't work. Checking the state machine viewer, the state machine using one-hot encoding style. If I only change encoding style to "gray" or "sequential", RTL code doesn't change. The state machine work correctly! What's the problem? How can I debug and prevent this problem? Environment : Quartus Prime Pro Edition 19.2. Thank you all.
Agilex 5 IOPLL Max Numbers and Tool Display Mismatch
Hello everyone Let me discuss the title. [Question] What is the maximum number of IOPLLs (Bank IOPLLs, Fabric Feeding IOPLLs, and perspective of whether System PLL can be used for other purpose ) on an A5EC008BB32AE5S, both device wide and bank/block wise? In particular, I would like to know the official opinion on how Quartus Pro Edition (Fitter/Report) and Power and Thermal Calculator count the upper limit on IO96B (HSIO) banks and the upper limit on HVIO blocks. Please check the attached file for details. Best Regards
IOPLL related clock constraints
Hello Every one I am struggling with creating clock constraint and need help. I have agilix 10 FPGA design at project level top module I have input "iopll_clk_clk". this input is mapped to clock capable input pin on FPGA and is connected to 50MHz on board clock source. The toplevel module has iopll instantiation as following pcie_ed_iopll_0 iopll_0 ( .refclk (iopll_clk_clk), // input, width = 1, refclk.clk .locked (), // output, width = 1, locked.export .rst (resetip_ninit_done_reset), // input, width = 1, reset.reset .outclk0 (iopll_0_outclk0_clk) // output, width = 1, outclk0.clk ); "iopll_0_outclk0_clk" is supposed to be used as clock input for inner logic only. in Platform designer IOPLL is IP is configured to output only one clock at 300MHz. in the project SDC file I have following constraints #iopll Clock create_clock -period 20 [get_ports iopll_clk_clk] #derive_pll_clocks -create_base_clocks - Tried it but not supported for Agilex 10 create_generated_clock -multiply_by 6 -source [get_ports iopll_clk_clk] -name iopll_0_outclk0 [get_pins iopll_0|iopll_0_outclk0] - this is line 17 Here while compiling the design during fitter stage i see following warning messages. Warning(332174): Ignored filter at intel_rtile_pcie_ed.sdc.terp(17): iopll_0|iopll_0_outclk0 could not be matched with a pin Warning(332049): Ignored create_generated_clock at intel_rtile_pcie_ed.sdc.terp(17): Argument <targets> with value [get_pins {iopll_0|iopll_0_outclk0}] contains zero elements This tells me that the IOPLL clocks are not constrained properly and Quartus wont be able to evaluate clock paths correctly for internally generated 300MHz clock. can you help me in figuring out what am i doing wrong here? How can I correctly constraint that iopll is fed with 50MHz clock and its output is 300MHz clock?
Quartus Prime Pro Hierarchy View has blank rows for some instances
Hello, I am using Quartus Prime Pro and after a compilation of my design, the Hierarchy view in the Project Navigator shows the board utilization metrics such as ALMs needed, DSP blocks, etc. I have noticed that some lines appear completely blank. I didn't initially believe these are due to components being synthesized out because these components that appear blank appear in the RTL viewer and my understanding was that the RTL Viewer wouldn't show the component if it was synthesized out. I am looking to confirm why some instances appear as blank items in the Hierarchy view. Is the tool taking advantage of resource sharing and therefore no new resources are used for that instance? Does the tool refrain from repeating data so that's why I have 1 instance with data and 2 others that are the same component without data? Is a blank cell and a 0 the same thing expressed differently depending on if the row as a whole was 0s? Is this just due to the tool not wanting to repeat itself because I've noticed I can get utilization metrics for instance_0 of a component but instance_1 and _2 of the same component are blank. Any subcomponents of a blank instance are also always blank as well. Normally there aren't many blank lines and the components were small enough for me to assume it was resource sharing, but with my current design, the components that are blank are seemingly pretty large and complicated so I'd like to learn more about how the tool is reporting and I haven't found an answer in your published documentation yet.
How to upgrade IP from Quartus 24.1 and add it to a Quartus 25.1 Project?
Hello ALTERA Quarts Experts, I have created and configured an ALT_PLL IP in Quartus Standard edition 24.1. Now i need to add that IP to a Quartus 25.1 Standard Edition project. I have tried this so far: added the IPs output files to my 25.1 project: readout_pll.qip, readout_pll.v, readout_pll_bb.v There is also a file called: readout_pll.ppf which appears to be an xml file. Not exactly sure what this is meant to do or if i also needed to add that? I then see the message from Quartus 25.1 asking me to do an auto IP upgrade, which id did and it was successful according to Quartus. But then i don't see the IP appear in the projects IP Catalogue even after i do an IP library refresh. Can anybody please tell me what else i need to do in order to be able to use the IP in my 25.1 Project ? I am having to do all this because the ALT_PLL symbol is all messed up and is unusable in Quartus Standard Edition 25.1. For That problem i have already created another post recently and have been assured this will be fixed. But for now until its fixed i need to do this IP upgrade. Thanks, BarryThe best way to implement SignalTapII
Hello Altera SigalTap Experts, I have been trying to use Signal Tap in my MAX10 FPGA with Quartus STD 25.1 project. I was trying to use the Signal Tap GUI at first. The problem seems to be that for the signals i want to add to my Signal Tap probes, even after i add a constraint such as: (* keep = "true" *) logic vio_init_source; for example in System Verilog on ALL the signals i want to see in Signal Tap, they keep getting synthesised away. So i don't see a lot of the signals i need post synthesis / post fitting. If i do a node search for them they either don't appear after the search OR if they appear and i try to add them to my Signal Tap probes list they appear in RED {meaning Signal Tap can't use them i guess}. Then you seem to be forced into doing a 'Rapid Recompilation' which in my experience always means that i need to do a full FPGA compilation. This seems a bit crazy when i already did a full FPGA compile to get to this stage in the first place and i did it with all my 'keep' constraints applied to all the signals i wanted to use with Signal Tap. I have also tried using the Signal Tap Instantiation in my RTL, but that method also has the same sort of problems. My Question is: what is the best method(s) to use to guarantee that Signal Tap can find my signals after doing a Synthesis and Fitting run ? The other question is that it seems (unlike with AMD/Xilinx VivadoScope) that every time i make a change to my trigger equation, signa tap needs to do a full recompile. This is surely wrong and a bit crazy too ! Signal Tap already knows all the signals i am using for my trigger logic so why does it need to do a full FPGA compile { or 'Rapid Recompilation' in Signal Tap speak } when i just change the trigger function ? Is there a better way to use Signal Tap to prevent this sort of behaviour ? Thanks for your help, Dr Barry H
