QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer
When I execute the Signal Tap Logic Analyzer function on QuartusPro 25.3, after finding and viewing the signal I wanted , then saving it, the crash was happend. I also saved the log by clicking "preview report". the part of log message as below. *** Fatal Error: Segment Violation: faulting address=(nil), PC=0x7f9af7f4acff : 0x7f9af7f4acff: sld_sdr!SDR_TX_SIGNAL_NODES_GEN2::get_parent_index(int, int) + 0x29 Module: quartus Stack Trace: Err Handler 0x327e1: ERR_UNWINDER_BACKTRACE::get_stack_trace(void const**, int, int, void*) + 0xed (ccl_err) Err Handler 0x8f7b0: msg_ie_get_call_stack(void*) + 0xc4 (ccl_msg) Err Handler 0x91b16: MSG_INTERNAL_ERROR::report_fatal(char const*, void*, bool) + 0x40 (ccl_msg) Err Handler 0x123c7: err_report_fatal_exception(char const*, void*, bool) + 0x63 (ccl_err) Err Handler 0x24f40: err_sigaction_handler + 0x727 (ccl_err) System 0xf630: (pthread)
Automatically added negative node for TDS output doesn't work with Agilex 5
Hello, I'm trying to build a basic SE to DE converter on Agilex 5 module SEtoDE ( input SE, output DE ); assign DE = SE; endmodule I assign respective IO standards and use locations chosen by Quartus Resulting in this .qsf assignments set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE Compilation on Quartus 25.3.1 however doesn't produce a programming file due to below listed warnings Critical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details. Critical Warning(15714): Some pins are missing I/O Standard assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------------------------------------------------------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; +----------+-----------------------------------------------------------------------------------------------+ There are essentially two kinds of warnings, both unexpected and only occuring with Agilex 5 (and also Agilex 3). With Agilex 7 or Cyclone 10 GX, the design compiles flawlessly. 1. Warnings for negative pin: Missing I/O standard etc. 2. Missing termination setting It turns out, that the problem can be fixed by adding an explicit I/O standard for the negative pin, although it shouldn't be required according to Quartus User Manual. Then the warning level reduces and programming files are generated Warning(25315): Some pins are missing drive strength (current strength) and/or slew rate assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Missing termination setting ; +----------+-----------------------------+ To remove this warning, we also need to assign dummy termination settings to the TDS outputs set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to DE -entity SEtoDE Presume this should never happen Regards FrankQuartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.error in JTAG server (error code 35) and autodetect (unable to scan device chain) Quartus 18.1
Hello fellow members, I have a Max10 FPGA Evaluation Kit board (10M08SAE144C8G) which i want to flash via JTAG. For this, i have installed Quartus Prime (18.1 version) and have USB Blaster 2 as an interface. After connecting the hardware, the LEDs on the board are stable. When i execute autodetect on the programmer , i get a dialog box stating "unable to scan device chain . Hardware is not connected"(screenshot attached). In the hardware setup , i coulkd see the usb blaster variant is added but still this error occurs. Similary when i try to run the .pof file , the diagnosis show "unexpected error in JTAG server -- error code 35" (screenshot attached). I checked the driver and it seems the USB blaster driver is also updated. On the command prompt, it shows 1) USB-Blaster variant [USB-1] Unable to lock chain - Hardware not attached Has someone encountered this issue before. Any help or suggestion would be highly appreciated. The screenshots can be seen in the attachments. Thanks. Best Regards, Ali
Quartus Eda_Writer keeps crashing
Quartus Prime v25 keeps crashing at the eda_writer step during the flow on Windows 11. I have tried different Quartus versions (II v13.1, Prime Lite v25, Prime Standard v25). All of them crashed at this step multiple times. Is this an issue with the design that I am trying to implement? I searched for this error on Google and I found a message that said it was a bug that was fixed in version 21.1. Strange that its still occuring now in v25 standard. Problem Details Error: Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_hierarchy_builder.cpp, Line: 1097 m_bp_manager != NULL Stack Trace: 0x48eca: WSC_HIERARCHY_BUILDER::build_map_from_partitions + 0x8a (NETO_WSC) 0x46dd5: WSC_HIERARCHY_BUILDER::build_hierarchy_from_partitions + 0x35 (NETO_WSC) 0x45e1b: WSC_HIERARCHY_BUILDER::build + 0x22b (NETO_WSC) 0x16282: QNETO_START::build_hierarchy_netlist + 0x242 (quartus_eda) 0x28548: QNETO_START::generate_simulation_files + 0x688 (quartus_eda) 0x1a1e3: QNETO_START::generate_eda_files + 0x43 (quartus_eda) 0x33fd0: qneto_execute + 0x210 (quartus_eda) 0xa79b: QNETO_FRAMEWORK::execute + 0x26b (quartus_eda) 0x10b5f: qexe_do_normal + 0x22f (comp_qexe) 0x16fa0: qexe_run + 0x420 (comp_qexe) 0x18012: qexe_standard_main + 0xb2 (comp_qexe) 0x10d17: qneto_main + 0x77 (quartus_eda) 0x12208: msg_main_thread + 0x18 (CCL_MSG) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x11a41: msg_exe_main + 0xa1 (CCL_MSG) 0x36423: __scrt_common_main_seh + 0x10b (quartus_eda) 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) 0x8c53b: RtlUserThreadStart + 0x2b (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 25.1std.0 Build: 1129 Edition: Standard Edition
Tensor block usage
The DSP_BLOCK_BALANCING is set to TENSOR, however, the final Flow Summary report doesn't report tensor blocks usage. Instead the DSP blocks show some usage. Also, none of the flow logs has any reference to the tensor blocks. It seems that Quartus Prime just ignored the DSP_BLOCK_BALACING setting! How can we force QP to target the tensor blocks and how to check if it did? Thanks
AGI027 Dev Kit example build takes a long time
I have a DK-DEV-AGI027-RA dev kit and am trying to build the pcie_ep example project in Quartus 25.3.1. I have had the spinning progress bar stuck at 0% for over 12 hours. It seems like it's stuck on the "IP Generation" step. Not sure if this is normal or something is wrong with my Quartus install or setup. Any help?Error(23098) when using IPM_IOPLL on Agliex 7
I am trying to use the IPM_IOPLL in my project on the Intel Agilex 7 FPGA I-Series Transceiver Development Kit (6x F-Tile) but whenever i use it i get the following error: Error(23098): One or more blocks are configured incorrectly and will not have the desired functionality. --BCM instance name: pio_0_2 Error(12274): A critical error occurred while the periphery placement was committed to the atom netlist. The atom netlist is now invalid and the Fitter must be restarted. Info(20273): Intermediate fitter snapshots will not be committed because ENABLE_INTERMEDIATE_SNAPSHOTS QSF assignment is disabled during compilation. Info(20274): Successfully committed planned database. Error: ERROR: An error occurred during automatic periphery placement Error: Quartus Prime Fitter was unsuccessful. 3 errors, 0 warnings Error: Peak virtual memory: 9478 megabytes Error: Processing ended: Tue Feb 24 11:20:55 2026 Error: Elapsed time: 00:01:22 Error: System process ID: 177973 Error(21794): Quartus Prime Full Compilation was unsuccessful. 5 errors, 109 warnings When i use an IOPLL generate from platform designer the project compiles successfully. The code for the IPM_IOPLL is below: inst_mac_iopll : IPM_IOPLL generic map( REFERENCE_CLOCK_FREQUENCY => "100.0 MHz", N_CNT => 1, M_CNT => 10, C0_CNT => 8, C1_CNT => 16, C2_CNT => 32, OPERATION_MODE => "direct", PLL_SIM_MODEL => "Agilex 7 (I-Series)" ) port map( refclk => clk, -- 100MHz input reset => g_rst_d1, outclk0 => i_mac_clk, -- 125MHz output outclk1 => mac_half_clk, -- 62.5MHz output outclk2 => i_ipb_clk, -- 31.25MHz output locked => i_locked ); I am not sure what is causing this error. I am using Quartus Prime Pro 24.3.1 with the DK-SI-AGI040FES board. Thanks
hps_sdram_p0_pin_assignments.tcl script failed
Hello, Quartus 25.1, Cyclone V, TCL script is failed with next messages. Please, help me to run it succesfully. source "D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_p0_pin_assignments.tcl" Error:Info: ******************************************************************* Error:Info: Running Quartus Prime Timing Analyzer Error: Info: Version 25.1std.0 Build 1129 10/21/2025 SC Standard Edition Error: Info: Copyright (C) 2025 Altera Corporation. All rights reserved. Error: Info: Your use of Altera Corporation's design tools, logic functions Error: Info: and other software and tools, and any partner logic Error: Info: functions, and any output files from any of the foregoing Error: Info: (including device programming or simulation files), and any Error: Info: associated documentation or information are expressly subject Error: Info: to the terms and conditions of the Altera Program License Error: Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Error: Info: the Altera IP License Agreement, or other applicable license Error: Info: agreement, including, without limitation, that your use is for Error: Info: the sole purpose of programming logic devices manufactured by Error: Info: Altera and sold by Altera or its authorized distributors. Please Error: Info: refer to the Altera Software License Subscription Agreements Error: Info: on the Quartus Prime software download page. Error: Info: Processing started: Mon Feb 23 16:23:09 2026 Error:Info: Command: quartus_sta -t D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_p0_pin_assignments.tcl DE10_NANO_SPI Error:Info: Quartus(args): DE10_NANO_SPI Error:Info: Cleaning up stale assignments... Error:Error (23031): Evaluation of Tcl script D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_p0_pin_assignments.tcl unsuccessful Error:Error: Quartus Prime Timing Analyzer was unsuccessful. 1 error, 0 warnings Error: Error: Peak virtual memory: 4670 megabytes Error: Error: Processing ended: Mon Feb 23 16:23:09 2026 Error: Error: Elapsed time: 00:00:00 Error: Error: Total CPU time (on all processors): 00:00:00 Error:------------------------------------------------ Error:ERROR: Can't run the Timing Analyzer (quartus_sta) -- Partition Merge (quartus_cdb --merge) failed or was not run. Run the Partition Merge (quartus_cdb --merge) successfully before running the Timing Analyzer (create_timing_netlist -post_map). Error: while executing Error:"create_timing_netlist -post_map" Error: invoked from within Error:"if { ! [ timing_netlist_exist ] } { Error: create_timing_netlist -post_map Error:}" Error: (file "D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_p0_pin_a..." line 174) Error:------------------------------------------------ Error: while executing Error:"exec $cmd -t [ info script ] $project_name " Error: invoked from within Error:"if { ![info exists quartus(nameofexecutable)] || ($quartus(nameofexecutable) != "quartus_sta" && $quartus(nameofexecutable) != "quartus_map") } { Error: pos..." Error: (file "D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_p0_pin_a..." line 110) Error: invoked from within Error:"_source D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_..." Error: ("uplevel" body line 1) Error: invoked from within Error:"uplevel 1 $cmd " Error: (procedure "source" line 5) Error: invoked from within Error:"source "D:/Folder/Terasic/DE10-Nano_v.1.1.0_HWrevE_SystemCD/Tools/SystemBuilder/CodeGenerated/DE10_NANO/DE10_NANO_SPI/db/ip/hps/submodules/hps_sdram_..."Quartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, Michael
