Proper way to infer Quad Port Ram?
I generated the Quad Port Template in Quartus 2025.3. I then wrapped it into a wrapper and finally into my design. This is then instantiated with the following generics: Info(19337): VHDL info at quad_port_ram.vhd(10): executing entity "quad_port_ram(data_width=578,addr_width=7)" with architecture "rtl" Info(19337): VHDL info at quad_port_ram.vhd(10): executing entity "quad_port_ram(data_width=578,addr_width=8)" with architecture "rtl" Info(19337): VHDL info at quad_port_ram.vhd(10): executing entity "quad_port_ram(data_width=578,addr_width=9)" with architecture "rtl" Info(19337): VHDL info at quad_port_ram.vhd(10): executing entity "quad_port_ram(data_width=578,addr_width=10)" with architecture "rtl" However I get the following errors: Warning(276002): Cannot convert all sets of registers into RAM megafunctions when creating nodes; therefore, the resulting number of registers remaining in design can cause longer compilation time or result in insufficient memory to complete Analysis and Synthesis Info(276012): RAM logic "stage_gen[13].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[12].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276014): Found 9 instances of uninferred RAM logic Info(276012): RAM logic "stage_gen[13].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[12].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[11].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[10].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[9].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[8].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[7].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[6].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Info(276012): RAM logic "stage_gen[5].pipe_fft_stage|math_fft_quad_port_ram_1_0_inst|quad_port_ram_inst|ram" is uninferred due to too many ports Is there something that can be done to properly infer quad-port ram in 25.3? Here's the VHDL generated from the template: -- Quartus Prime VHDL Template -- Quad Port RAM with separate read/write addresses and -- single read/write clock -- This style of RAM cannot be used on Arria 10, -- which does not support Quad Port RAM library ieee; use ieee.std_logic_1164.all; entity quad_port_ram is generic ( DATA_WIDTH : natural := 2; ADDR_WIDTH : natural := 6 ); port ( clk : in std_logic; read_addr_a : in natural range 0 to 2**ADDR_WIDTH - 1; read_addr_b : in natural range 0 to 2**ADDR_WIDTH - 1; write_addr_a : in natural range 0 to 2**ADDR_WIDTH - 1; write_addr_b : in natural range 0 to 2**ADDR_WIDTH - 1; data_a : in std_logic_vector((DATA_WIDTH-1) downto 0); data_b : in std_logic_vector((DATA_WIDTH-1) downto 0); we_a : in std_logic := '1'; we_b : in std_logic := '1'; q_a : out std_logic_vector((DATA_WIDTH -1) downto 0); q_b : out std_logic_vector((DATA_WIDTH -1) downto 0) ); end quad_port_ram; architecture rtl of quad_port_ram is -- Build a 2-D array type for the RAM subtype word_t is std_logic_vector((DATA_WIDTH-1) downto 0); type memory_t is array(2**ADDR_WIDTH-1 downto 0) of word_t; -- Declare the RAM shared variable ram : memory_t; begin -- Port A process(clk) begin if(rising_edge(clk)) then if(we_a = '1') then ram(write_addr_a) := data_a; end if; end if; end process; process(clk) begin if(rising_edge(clk)) then q_a <= ram(read_addr_a); end if; end process; -- Port B process(clk) begin if(rising_edge(clk)) then if(we_b = '1') then ram(write_addr_b) := data_b; end if; end if; end process; process(clk) begin if(rising_edge(clk)) then q_b <= ram(read_addr_b); end if; end process; end rtl;
Quartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, Michael
NIOS V Sysnthesis Fails with Quartus 25.1 Lite
Hi, I used Quartus 23.1 Lite for a couple of months and have now switched to Quartus 25.1 Lite. Since the version update my NIOS V Plattform Designer Projects do not synthesize any longer. Synthesis fails with: Info (12128): Elaborating entity "niosv" for hierarchy "niosv:u0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0" Info (12128): Elaborating entity "niosv_intel_niosv_m_0_hart" for hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Error (10835): SystemVerilog error at riscv.pkg.sv(149): no support for unions Error (10835): SystemVerilog error at riscv.pkg.sv(333): no support for unions Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1163): encoded value for element "MXL32" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1164): encoded value for element "MXL64" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1165): encoded value for element "MXL128" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1167): encoded value for element "MXL_RESERVED" has width 32, which does not match the width of the enumeration's base type (2) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1233): encoded value for element "INSTRUCTION_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1234): encoded value for element "INSTRUCTION_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1235): encoded value for element "ILLEGAL_INSTRUCTION" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1236): encoded value for element "BREAKPOINT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1237): encoded value for element "LOAD_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1238): encoded value for element "LOAD_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1239): encoded value for element "STORE_AMO_ADDRESS_MISALIGNED" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1240): encoded value for element "STORE_AMO_ACCESS_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1241): encoded value for element "USER_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1242): encoded value for element "SUPERVISOR_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1243): encoded value for element "MACHINE_ECALL" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1244): encoded value for element "INSTRUCTION_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (10355): SystemVerilog Enumeration Type Declaration error at riscv.pkg.sv(1245): encoded value for element "LOAD_PAGE_FAULT" has width 32, which does not match the width of the enumeration's base type (5) Error (12152): Can't elaborate user hierarchy "niosv:u0|niosv_intel_niosv_m_0:intel_niosv_m_0|niosv_intel_niosv_m_0_hart:hart" Info (144001): Generated suppressed messages file /home/simon/Documents/QuartusPrime/MAX10_InternalFlash_Ticket/output_files/MAX10_InternalFlash_Ticket.map.smsg Error: Quartus Prime Analysis & Synthesis was unsuccessful. 20 errors, 30 warnings Error: Peak virtual memory: 369 megabytes Error: Processing ended: Mon Nov 10 09:24:51 2025 Error: Elapsed time: 00:00:39 Error: Total CPU time (on all processors): 00:01:41 Error (293001): Quartus Prime Full Compilation was unsuccessful. 22 errors, 30 warnings I am using the DE10-Lite Board with the Golden Top example Design and add a very basic Nios V to it. //======================================================= // Structural coding //======================================================= niosv u0 ( .clk_clk (MAX10_CLK1_50), // clk.clk .reset_reset_n (1'b1) // reset.reset_n ); Any idead how I can fix that Issue? Best regards Simon
Error (19021): The same file name "clock_in_0" is used for different IP files
Hello All! Im curious how one fixes a hierarchical QSYS system related quartus compile error like the following given that the name "clock_in_0" was not chosen by the designer, but instead by platform designer, and is not something we can change in the Platform Designer GUI? Is it necessary to hand edit the IP or QSYS/IP XML giberish files to fix such issues? Given no other options that is probably what I will beforced to try next. Thanks! (/ade/fpga/altera/pro_22.4/quartus/sopc_builder/bin/qsys-generate ../../../top/ioc/fcm2_ioc.qsys --search-path="../../../pins, ../../../top, ../../../top/ioc, .., $" --family="Arria 10" --part=10AX066K4F40E3SG --synthesis=VHDL --clear-output-directory --jvm-max-heap-size=64g --quartus-project=fcm2 --rev=fcm2_adc || echo "cmd-fail-status" $?) |& perl ../../../../../../../build-sys/filter_quartus.pl qsysgen fcm2_ioc_qsys_gen_failed.log Ignoring env var, _JAVA_OPTIONS="-Xmx64g" Please use env var, QSYS_EDIT_JVM_ARGS, to apply your JVM arguments to Qsys Pro *************************************************************** Quartus is a registered trademark of Intel Corporation in the US and other countries. Portions of the Quartus Prime software code, and other portions of the code included in this download or on this DVD, are licensed to Intel Corporation and are the copyrighted property of third parties. For license details, refer to the End User License Agreement at http://fpgasoftware.intel.com/eula. *************************************************************** mv fcm2_ioc_qsys_gen_failed.log fcm2_ioc_qsys_gen.log (/ade/fpga/altera/pro_22.4/quartus/bin/quartus_sh --no_banner --flow compile fcm2 -c fcm2_adc || echo "cmd-fail-status" $?) |& perl ../../../../../../../build-sys/filter_quartus.pl quartus fcm2.compile.log Error (19021): The same file name "clock_in_0" is used for different IP files. The same name cannot be used for more than one IP file. Only directly include the .ip file, not the .qip or .qsys. Error (22175): file: "top/ioc/ip/fcm2_adcs/clock_in_0.ip" Error (22175): file: "top/ioc/ip/fcm2_periph/clock_in_0.ip" Error: Flow failed: 0x20c47a40 Error: Quartus Prime Synthesis was unsuccessful. 4 errors, 129 warnings Error: Peak virtual memory: 3496 megabytes Error: Processing ended: Wed Nov 12 09:58:48 2025 Error: Elapsed time: 00:01:01 Error: System process ID: 2072199 Error (21794): Quartus Prime Full Compilation was unsuccessful. 6 errors, 224 warnings Error: Flow compile (for project integration/adc/O.quar.prod/fcm2) was not successful Error: run_flow flow:run1 finished: 0 Failed Error (23031): Evaluation of Tcl script /ade/fpga/altera/pro_22.4/quartus/common/tcl/internal/qsh_flowengine.tcl unsuccessful Error: Quartus Prime Shell was unsuccessful. 13 errors, 224 warnings Error: Peak virtual memory: 1310 megabytes Error: Processing ended: Wed Nov 12 09:58:54 2025 Error: Elapsed time: 00:03:54 Error: System process ID: 2068912
dut.p0_hip_status has no associated reset.
Hello Altera I am using Quartus Prime Pro 25.1.0 build 129 03/26/2025 SC Pro Edition. In my Agiliex 7 Design project, I have Intel R-Tile MCDMA for PCI Express intel_pcie_rtile_mcdma Version 5.3.1 Ip instantiated as "dut". in parameters settings I have enabled to have hip status interface. this interface is connected to a custom design QCP file. The QCP uses "app_clk" and "app_nreset_status" from dut ip as its clk and reset inputs. THey go through clock bridge and reset bridge. Clock and reser outputs from these bridges are used internally in QCP creation In platform designer as I connect "dut.p0_hip_status" and "custom_module_pcie_ep_hip_status_in" I get an error as following "Error: pcie_ed: Interfaces custom_module_pcie_ep_hip_status_in and dut.p0_hip_status must have matching associated resets, but dut.p0_hip_status has no associated reset." This Error does not make sense to me, as dut`s hip status interface and my qcp`s status interface ports shows correct clock and reset association in component instantiation tab; and my custom design uses same clock and reset to its clock and reset bridge inputs. can you please help me to understand what is this error about and how do i resolve it?
How to upgrade IP from Quartus 24.1 and add it to a Quartus 25.1 Project?
Hello ALTERA Quarts Experts, I have created and configured an ALT_PLL IP in Quartus Standard edition 24.1. Now i need to add that IP to a Quartus 25.1 Standard Edition project. I have tried this so far: added the IPs output files to my 25.1 project: readout_pll.qip, readout_pll.v, readout_pll_bb.v There is also a file called: readout_pll.ppf which appears to be an xml file. Not exactly sure what this is meant to do or if i also needed to add that? I then see the message from Quartus 25.1 asking me to do an auto IP upgrade, which id did and it was successful according to Quartus. But then i don't see the IP appear in the projects IP Catalogue even after i do an IP library refresh. Can anybody please tell me what else i need to do in order to be able to use the IP in my 25.1 Project ? I am having to do all this because the ALT_PLL symbol is all messed up and is unusable in Quartus Standard Edition 25.1. For That problem i have already created another post recently and have been assured this will be fixed. But for now until its fixed i need to do this IP upgrade. Thanks, Barry
Ashling RiscFree Build Error
Hi, I am using Pro version 25.1 and Ashling RiscFree 25.1. I have found a difference between staring RiscFree from the Windows icon and from the Nios V command line. This is a known problem that was supposed to have been fixed in version 22.3. (see below). Is it back? https://www.intel.com/content/www/us/en/support/programmable/articles/000091393.html Please see the two attachments for building the same project after starting RiscFree using two different methods. Anyone else seeing this? Thanks
