compilation

241 Topics

How can I use Quartus Pro 25.1 sopc-create-header-files tool to generate a jtag master header file?
I am an engineer in Terasic, I am writting a tutorial for Agilex 5. I use Quartus Pro 25.1, there is a sopc-create-header-files in \quartus\sopc_builder\bin path, I want to generate a header file in Windows system.however, I couldn't use it in Win10 system. I tried it in Nios V command Shell: even I used Windows WSL: or in Windows PowerShell： Thanks for your advice. Doreen
DLiu5
1 day ago Place Quartus® Prime
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Intermittent DDM Errors
Hi Everyone, Beginning January 10, 2026, executing commands in the terminal or GUI of Quartus Prime Pro Edition software, Quartus Embedded Edition software, or select standalone tools may cause the software or tool to crash. This error affects: Quartus Prime Pro Software versions v23.3 through v25.3.1 Standalone Quartus Prime Pro Programmer v23.3 through v25.3.1 Standalone Quartus Prime Pro Embedded Edition v25.3 and 25.3.1 Standalone Quartus Prime Pro Power Thermal Analyzer v25.3 through v25.3.1 This issue is not observed in Quartus Prime Pro Edition versions 23.2 or prior or Quartus Prime Standard Edition. For more information, see this KDB: Why do I unexpectedly observe intermittent DDM Errors? | Altera Community Sue
SueC_Altera
1 day ago Place Quartus® Prime
244Views
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5Comments
Agilex 5 – Critical HSSI Error in JESD204B Example Design
Hi, I am bringing up the JESD204B interface on the dev kit. For this, I used the "Generate Example Design" option with the following parameters: When I generate the project and start synthesis, it reaches the "HSSI Support Logic Generation" stage, and Quartus reports the following critical error: It turns out that the generated file contains an inconsistency in the generated HSSI metadata. My fix was to replace the entry in: The problem is that after updating the Qsys file, it gets changed back to intel_jesd_RX, and HSSI reports the critical error again. If there is already a fix or workaround for this issue, please let me know. For now, I added a simple script that I run from PowerShell: that replaces this value with the correct one:
robertzab
8 days ago Place Quartus® Prime
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Generating RBF raw binary file on Max 10
I am trying to design an in-system firmware update for the Max 10 FPGA. I have a microcontroller between the FPGA and the outside world. The microcontroller has a large data storage area where I want to store the data for the new FPGA firmware. I want to load the data into there, then at some later time, have the microcontroller take care of sending the update to the FPGA. In the interest of modular design, I want to store the data in a generic or raw format. This will give the microcontroller the option of bit-banging the JTAG of the FPGA, or sending over any other communication channel. However, I am not able to find a way to get the raw data that goes into the CFM0 section of the FPGA's configuration flash. When I compile the FPGA's firmware, I get the SOF and POF files. I am able to use the POF file directly with USB Blaster as usual. However, these file formats are apparently not public information, so I can't reliably build my own tool for extracting the raw data. So I started looking into the available utilities in the Quartus software. In the Quartus Programmer, I looked at File -> Create JAM, JBC, SVF, ISC. All of these formats basically generate a file containing a list of JTAG instructions. Because I want the design to be modular, I do not want to use this directly and be locked into JTAG. Since these formats are documented, I think it would be possible to build my own post-build tool that emulates the receiving end of JTAG and extracts raw data from one of these formats. However, I would like to get the raw data directly somehow in order to minimize risk of error building my own tool like that. So I confinued looking elsewhere to get the raw data. Next, in the Quartus IDE, I found File -> Convert Programming Files. This utility can generate an RBF file (Raw Binary File), which is EXACTLY what I need. I selected output file type "Raw Binary File (.rbf)", selected the compiled SOF file as the input, and clicked Generate. This gives me the vague error message "Device 10M02SCE144 does not support selected configuration mode". Playing around with lots of settings, I never could get it to generate an RBF file for me. I was searching the internet how to do this. Ideally, I wanted a command line way of generating the file so I can do this with a post-build script and have the ability for a build server to do this, etc. I found some instructions using the Quartus Nios II Command Shell. It seemed I needed to install a full distribution of Linux on my PC in order to use the shell... Not willing to do that (I am running Windows 11), I did some more digging, and I found the actual EXE file on my hard drive that the command shell stuff was going to run for me, "quartus_cpf.exe". I ran it like this: quartus_cpf.exe -c firmware.sof firmware.rbf It still failed, but now I get a slightly better error message: Device 10M02SCE144 does not support 1-bit Passive Serial scheme Error (213050): Convert Programming Files was NOT successful -- refer to messages that appear above this message for more information Error: Quartus Prime Convert_programming_file was unsuccessful. 1 error, 0 warnings After all of that, I am still stuck. How can I properly get to the raw binary format for the CFM0 memory?
Solved
Dennis_Nedry
11 days ago Place Quartus® Prime
59Views
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5Comments
Quartus/Signaltap complains about wrong version
Hello, we are using Quartus prime V24.1.0 for a rather large project. We have various signaltap files stored within git for analysis. Now, from time to time, it happens that quartus throws the following warning/assertion. Obviously, this assertion can be suppressedwith ENABLE_VHDL_STATIC_ASSERTIONS OFF, and everything is working. However this is no soulution as we want to have ENABLE_VHDL_STATIC_ASSERTIONS ON Error (22148): VHDL error at sld_ela_control.vhd(1263): Failure: "The design file sld_ela_control.vhd is released with Q uartus Prime software Version 24.1.0. It is not compatible with the parent entity. If you generated the parent entity us ing the Signal Tap megawizard, then you must update the parent entity using the megawizard in the current release.": exi ting elaboration File: c:/intelfpga_pro/24.1/quartus/libraries/megafunctions/sld_ela_control.vhd Line: 1263 If I remove the signaltap(file) entirely, and readd it, everything works. However, this is very annoying and time consuming. Q1. Why is this assertion triggered in the first place? We do not use any other versions. Q2. How do I "update the parent entity using the megawizard"? I'm unable to find an "update" option. To me deleting signaltap and re-creating it is not an update.... Thanks, Michael
MichaelL
22 days ago Place Quartus® Prime
277Views
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21Comments
Automatically added negative node for TDS output doesn't work with Agilex 5
Hello, I'm trying to build a basic SE to DE converter on Agilex 5 module SEtoDE ( input SE, output DE ); assign DE = SE; endmodule I assign respective IO standards and use locations chosen by Quartus Resulting in this .qsf assignments set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE Compilation on Quartus 25.3.1 however doesn't produce a programming file due to below listed warnings Critical Warning(25207): A programming file will not be generated because the assembler identified some pins have missing I/O Standard assignments. Refer to the I/O Assignment Warnings table in the fitter report for details. Critical Warning(15714): Some pins are missing I/O Standard assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------------------------------------------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------------------------------------------------------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------------------------------------------------------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Incomplete set of assignments. Missing I/O standard, drive strength and slew rate assignments ; +----------+-----------------------------------------------------------------------------------------------+ There are essentially two kinds of warnings, both unexpected and only occuring with Agilex 5 (and also Agilex 3). With Agilex 7 or Cyclone 10 GX, the design compiles flawlessly. 1. Warnings for negative pin: Missing I/O standard etc. 2. Missing termination setting It turns out, that the problem can be fixed by adding an explicit I/O standard for the negative pin, although it shouldn't be required according to Quartus User Manual. Then the warning level reduces and programming files are generated Warning(25315): Some pins are missing drive strength (current strength) and/or slew rate assignments. Refer to the I/O Assignment Warnings report for details. +----------------------------------------+ ; I/O Assignment Warnings ; +----------+-----------------------------+ ; Pin Name ; Reason ; +----------+-----------------------------+ ; DE ; Missing termination setting ; ; DE(n) ; Missing termination setting ; +----------+-----------------------------+ To remove this warning, we also need to assign dummy termination settings to the TDS outputs set_global_assignment -name DEVICE A5EC008BM16AE6S set_location_assignment PIN_AJ24 -to SE -comment IOBANK_5A set_location_assignment PIN_D13 -to DE -comment IOBANK_3A_B set_location_assignment PIN_C12 -to "DE(n)" -comment IOBANK_3A_B set_instance_assignment -name IO_STANDARD "3.3-V LVCMOS" -to SE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to DE -entity SEtoDE set_instance_assignment -name IO_STANDARD "1.3-V TRUE DIFFERENTIAL SIGNALING" -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to "DE(n)" -entity SEtoDE set_instance_assignment -name OUTPUT_TERMINATION OFF -to DE -entity SEtoDE Presume this should never happen Regards Frank
FvM
24 days ago Place Quartus® Prime
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6Comments
Quartus 20.1std compilation fails for Quartus map - Device 10AS057K2F40I1SG
Hi Chandu sri, We will continue the discussion here. Issue Chandu Sri is facing compilation errors in Quartus when working with the Arria 10 device (10AS057K2F40I1SG/10AS057K2F40I1HG) and HPS IP, both in Quartus Standard and Pro editions (20.1std, 24.1Std, 25.1.1pro). Errors include unsupported device messages, out-of-range configuration values, and Tcl script issues when generating the HPS IP core. The Arria 10 device is flagged as deprecated in the Standard version; IP core generation fails in Pro edition as well. Example design generation is disabled for krpi_pcie.qsys; krpi_hps.qsys IP core creation fails with multiple errors. Actions Taken Device was changed from 10AS057K2F40I1SG to 10AS057K2F40I1HG, but errors persist. Attempted manual recreation of the IP cores in 25.1.1pro instead of upgrading legacy designs. Provided .qar file and detailed error logs to Intel support for further analysis. Next Steps / Recommendations Intel support (Kenny) has requested the .qar file for investigation. Suggested complete deletion and manual re-creation of the problematic HPS IP in Platform Designer. Discussion may continue on the Intel community forum if needed.
KennyT_altera
25 days ago Place Quartus® Prime
413Views
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34Comments
error in JTAG server (error code 35) and autodetect (unable to scan device chain) Quartus 18.1
Hello fellow members, I have a Max10 FPGA Evaluation Kit board (10M08SAE144C8G) which i want to flash via JTAG. For this, i have installed Quartus Prime (18.1 version) and have USB Blaster 2 as an interface. After connecting the hardware, the LEDs on the board are stable. When i execute autodetect on the programmer , i get a dialog box stating "unable to scan device chain . Hardware is not connected"(screenshot attached). In the hardware setup , i coulkd see the usb blaster variant is added but still this error occurs. Similary when i try to run the .pof file , the diagnosis show "unexpected error in JTAG server -- error code 35" (screenshot attached). I checked the driver and it seems the USB blaster driver is also updated. On the command prompt, it shows 1) USB-Blaster variant [USB-1] Unable to lock chain - Hardware not attached Has someone encountered this issue before. Any help or suggestion would be highly appreciated. The screenshots can be seen in the attachments. Thanks. Best Regards, Ali
Ali789
25 days ago Place Quartus® Prime
52Views
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2Comments
QuartusPro 25.3 Crashed after using the Signal Tap Logic Analyzer
When I execute the Signal Tap Logic Analyzer function on QuartusPro 25.3, after finding and viewing the signal I wanted , then saving it, the crash was happend. I also saved the log by clicking "preview report". the part of log message as below. *** Fatal Error: Segment Violation: faulting address=(nil), PC=0x7f9af7f4acff : 0x7f9af7f4acff: sld_sdr!SDR_TX_SIGNAL_NODES_GEN2::get_parent_index(int, int) + 0x29 Module: quartus Stack Trace: Err Handler 0x327e1: ERR_UNWINDER_BACKTRACE::get_stack_trace(void const**, int, int, void*) + 0xed (ccl_err) Err Handler 0x8f7b0: msg_ie_get_call_stack(void*) + 0xc4 (ccl_msg) Err Handler 0x91b16: MSG_INTERNAL_ERROR::report_fatal(char const*, void*, bool) + 0x40 (ccl_msg) Err Handler 0x123c7: err_report_fatal_exception(char const*, void*, bool) + 0x63 (ccl_err) Err Handler 0x24f40: err_sigaction_handler + 0x727 (ccl_err) System 0xf630: (pthread)
Murray
26 days ago Place Quartus® Prime
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Quartus Eda_Writer keeps crashing
Quartus Prime v25 keeps crashing at the eda_writer step during the flow on Windows 11. I have tried different Quartus versions (II v13.1, Prime Lite v25, Prime Standard v25). All of them crashed at this step multiple times. Is this an issue with the design that I am trying to implement? I searched for this error on Google and I found a message that said it was a bug that was fixed in version 21.1. Strange that its still occuring now in v25 standard. Problem Details Error: Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_hierarchy_builder.cpp, Line: 1097 m_bp_manager != NULL Stack Trace: 0x48eca: WSC_HIERARCHY_BUILDER::build_map_from_partitions + 0x8a (NETO_WSC) 0x46dd5: WSC_HIERARCHY_BUILDER::build_hierarchy_from_partitions + 0x35 (NETO_WSC) 0x45e1b: WSC_HIERARCHY_BUILDER::build + 0x22b (NETO_WSC) 0x16282: QNETO_START::build_hierarchy_netlist + 0x242 (quartus_eda) 0x28548: QNETO_START::generate_simulation_files + 0x688 (quartus_eda) 0x1a1e3: QNETO_START::generate_eda_files + 0x43 (quartus_eda) 0x33fd0: qneto_execute + 0x210 (quartus_eda) 0xa79b: QNETO_FRAMEWORK::execute + 0x26b (quartus_eda) 0x10b5f: qexe_do_normal + 0x22f (comp_qexe) 0x16fa0: qexe_run + 0x420 (comp_qexe) 0x18012: qexe_standard_main + 0xb2 (comp_qexe) 0x10d17: qneto_main + 0x77 (quartus_eda) 0x12208: msg_main_thread + 0x18 (CCL_MSG) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x11a41: msg_exe_main + 0xa1 (CCL_MSG) 0x36423: __scrt_common_main_seh + 0x10b (quartus_eda) 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) 0x8c53b: RtlUserThreadStart + 0x2b (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 25.1std.0 Build: 1129 Edition: Standard Edition
palaparthy
1 month ago Place Quartus® Prime
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7Comments