Quartus 22.1 and 23.1 Synthesis Error
Hi, I am currently working on a project targeting a Cyclone V device using Quartus Prime versions 22.1 and 23.1. The design compiles and functions correctly with no issues. However, after adding an FFT IP core, Quartus frequently fails during synthesis with the error shown below. The issue is reproducible in both Quartus versions. Interestingly, the compilation succeeds only intermittently (approximately once every 5–6 attempts), while most synthesis runs fail. Another observation is that if I change the Synthesis Effort setting to Fast, the design compiles successfully every time. Has anyone encountered similar behaviour or have any suggestions on how to work around this issue? Thanks in advance.78Views0likes3CommentsHow to fix Error(23782): Failed to find an expected report
Hey Altera Community I was messing around in the Board and IP settings trying to get simulation to work, but something went wrong and now I get this error every time I try to compile. How to fix? Info: Finished generating IP file(s) in the project. Error(23782): Failed to find an expected report while writing reporting database. Error: Quartus Prime IP Generation Tool was unsuccessful. 1 error, 6 warningsSolved138Views0likes4Commentsquartus pro 25.3 bug?
Now I am developing a project with agilex7 base on the quartus pro 25.3. the project contains R-TILE pcie hard ip and F-tile ethernet hard ip. During board bring-up debugging, we frequently encounter non-deterministic discrepancies between actual hardware behavior and simulation results. For instance, on a certain platform, the PCIe device fails to be enumerated by the host. Probing the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. However, we have verified that no traffic is being sourced to this interface, meaning these two signals should theoretically remain idle without constant toggling. And the timing of the project is cleaning. How should we proceed to troubleshoot this issue? Should we try upgrading the Quartus version as a potential solution?45Views0likes5CommentsQuartus crashes on long carry chain in Agilex 5 FPGAs
We try to manually place a carry chain in the Agilex 5 FPGAs which consists of more than 40 LABs. When we place this carry chain using set_location_assignment, Quartus crashes during the placement phase whenever the carry chain is longer than 40 LABs. Is it expected that the carry chain cannot be made longer than 40 LABs in the Agilex 5 FPGAs? Crash was observed on Quartus 25.3 and Quartus 26.1 for the devices A5ED065BB32AE4S and A5ED013BB32AE4SCS. Internal Error: Sub-system: FLABS, File: /quartus/fitter/flabs/flabs_util.cpp, Line: 96 p_to_fill->next == FLABS_OPEN82Views0likes3CommentsConnection bit order between hierarchy
Hi, I got unintended bit order of bus connection between SystemVerilog top with Block Design in lower hierarchy. I intend to connect inst3 to out[3] but Quartus connected in reversed order. Please see Technology map viewer screen shot and open archived project. Is there any Quartus option to fix this problem? This happens with (System)Verilog top only. I already experiment bdf, tdf, vhd top instead of sv, they work as expected. I am using Quartus Pro 23.2. Thanks, MasaruSolved356Views0likes9CommentsNIOS-V Shell: qsys-generate not found
Hello, we are using makefiles to build our Quartus & QSYS projects. Since we switched from NIOS-II shell to NIOS-V shell, I realized that qsys-generate is no longer accesible. The command "qsys-generate.exe" is either misspelled or was not found. Other quartus commandline tools remain available in NIOS-V Shell: quartus_sh/quartus_sh.exe quartus_fit/quartus_fit.exe The command qsys-generate.exe does exist, it is simple not added to the path in NIOS-V shell. What is the correct way to invoke qsys-generate.exe from within NIOS-V shell? best regards FabianSolved61Views0likes5Commentstiming impact
I performed compilation on two separate servers(A and B)using identical RTL source code and identical project configurations; however, the resulting timing violations differ between the two builds, with one server A has less timing violations. Does a server with more CPU cores, higher clock speed and bigger RAM help improve project timing results?Solved277Views0likes4CommentsHow to generate a netlist when the design includes encrypted sources
I would like to ship my design to a customer as an encrypted netlist, however I am unable to create the netlist after a successful run, because my design includes encrypted RTL (unable to change this). I am running the following command (after running synthesis and P&R): quartus_eda my_project --simulation --format=vhdl --tool=modelsim -c my_project_revision I get the following error: Error (18580): Cannot generate netlist output files because the design includes encrypted source files: "/path/to/encrypted/rtl/file.vhdp" I see here that this was planned to be possible in "future" Quartus Prime updates, but I am using 26.1 and no such update has been made. I have also attempted to run the following command, with the exact same result: quartus_eda my_project --resynthesis --tool=modelsim Any help would be appreciated; perhaps this is plainly impossible, or perhaps there is some work-around. Thank you!Solved122Views0likes3Comments