Forum Discussion
Occasional Contributorquartus pro 25.3 bug?
Now I am developing a project with agilex7 base on the quartus pro 25.3. the project contains R-TILE pcie hard ip and F-tile ethernet hard ip.
During board bring-up debugging, we frequently encounter non-deterministic discrepancies between actual hardware behavior and simulation results. For instance, on a certain platform, the PCIe device fails to be enumerated by the host. Probing the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. However, we have verified that no traffic is being sourced to this interface, meaning these two signals should theoretically remain idle without constant toggling.
And the timing of the project is cleaning. How should we proceed to troubleshoot this issue? Should we try upgrading the Quartus version as a potential solution?
5 Replies
RongY_alteraContributor
Hi,
This is more related to the SI issue. You can use a stp to check if LTSSM is failed and where it fails. You should run the PCIe test only when the link is stable.
Regards,
Rong
- zjj
we already use stp to check ltssm status and ltssm status is in L0/L1 that belong to normal state.
however, we find the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. and we have verified that no traffic is being sourced to this interface,
- RongY_altera
I tested R-Tile PCIe Gen5 1x16 with a AVST PIO design on Q25.3.1 Pro. My stp doesn't see any toggling on tx_stX_hvalid and rx_stX_dvalid signals.
On the problem board, I suggest you to test a PCIe only design first. Pls check your qsf to make sure PCIe related pins are correctly constrained before compilation. After system boots up, confirm the LTSSM is stable, i.e. not toggling, and link speed & width is correct. Before the application runs, the hvalid and dvalid signals are expected to stay LOW.
Regards,
Rong
