Forum Discussion
Occasional Contributorquartus pro 25.3 bug?
Occasional Contributorwe already use stp to check ltssm status and ltssm status is in L0/L1 that belong to normal state.
however, we find the Avalon-ST TX interface of the PCIe hard IP reveals continuous toggling on both the hvld and dvalid signals. and we have verified that no traffic is being sourced to this interface,
ContributorI tested R-Tile PCIe Gen5 1x16 with a AVST PIO design on Q25.3.1 Pro. My stp doesn't see any toggling on tx_stX_hvalid and rx_stX_dvalid signals.
On the problem board, I suggest you to test a PCIe only design first. Pls check your qsf to make sure PCIe related pins are correctly constrained before compilation. After system boots up, confirm the LTSSM is stable, i.e. not toggling, and link speed & width is correct. Before the application runs, the hvalid and dvalid signals are expected to stay LOW.
Regards,
Rong
- zjj
accorind to r-tile avalon streaming IP user guide, the slow_clk is sync to coreclkout_hip. But during test on-board, we find that the slow_clk and coreclkout_hip may lost sync sometimes. so how to debug further?
- RongY_altera
I checked the PIO design and these two clocks you mentioned are from different sources, unlike what I've experienced in other designs.
You can use a known user clock, normally 50MHz or 100MHz, to sample these two clocks, and monitor them with Transitional Type in a stp to record the changes. To check if they really lose sync, when the situation happens, and how frequent it happens.
Also pls make sure the OSC clock is set in your project.
Regards,
Rong
