Agilex 5 IOPLL Max Numbers and Tool Display Mismatch
Hello everyone Let me discuss the title. [Question] What is the maximum number of IOPLLs (Bank IOPLLs, Fabric Feeding IOPLLs, and perspective of whether System PLL can be used for other purpose ) on an A5EC008BB32AE5S, both device wide and bank/block wise? In particular, I would like to know the official opinion on how Quartus Pro Edition (Fitter/Report) and Power and Thermal Calculator count the upper limit on IO96B (HSIO) banks and the upper limit on HVIO blocks. Please check the attached file for details. Best Regards
[Agilex 7F] How to setup my EMIF IPs for the toolkit?
Hi, I've been trying to reconfigure my existing EMIF IPs to make them reachable from the EMIF toolkit and be able to generate some eye diagrams. The topology I have : 2x EMIF calib IPs 7x EMIF IPs One calib IP is connected to 3 EMIFs and the other to the 4 remaining. For the calib IPs, I selected "Add EMIF Debug Interface". For the EMIFs I did not do anything since "Note: Calibration Debug Options are set from EMIF Calibration IP which applies to all EMIFs connected to an I/O row". When opening the system console, I can see the instances in the System Explorer tab, but not in the Toolkit Explorer (I loaded the sof file). Am I doing something wrong? Note that I DO NOT want to start again from an example design, or let me know if it won't change anything for me in terms of settings, behavior, ... Also, if there's a way to generate the eye diagram "by hand" from the exported cal_debug port, I am more than interested. If there's any other way to automate the process of generating the eye diagrams, I would also be interested! Thanks!How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, AlkeshQSYS 25.3pro failed to generate VHDL simulation files for altera_remote_update_core
Hello, If I use altera_remote_update_core in a QSYS project using Quartus Version 25.3pro, the IP Generation fails with the following error message Info: sib_flash_subsys_remote_update_0: "Generating: altera_remote_update_core" Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Despite the error message being not very meaningful, I realized, that this fails only, when I select Simulation Model "VHDL". If I select simulation model "none" or "verilog" IP Generation works fine. The error is reproduceable by a simple QSYS project, which only contains altera_remote_update IP core. The error only occurs in Quartus 25.3pro. Using the exactly same project with Quartus 24.1pro works without error. Please advice, I would appreciate any help on this topic. Thanks best regards Fabian
Quartus Pro 25.3 Not showing HPS IO in Pin Planner
Hello, I have an Agilex-5 SoC design where the HPS IO pins I’ve assigned (UART, I2C, SD/MMC, etc.) are not appearing in the All Pins view in the Pin Planner, even with the filter set to “Pins: All.” Is this expected behavior, or is there another filter or setting I should adjust to view the HPS IO pins in the Pin Planner? Thank you, DanHard Reset Required After Each Boundary Scan Operation
Hello there, I am working on a project involving JTAG operations (specifically boundary scan on the data register) using Quartus Prime Standard (v24) and a USB-Blaster cable. Issue: After every scan operation, I need to perform a hard reset on the device connected to the cable. If I skip the hard reset, the next scan returns incorrect TDO values. I have tried performing a soft reset after each operation, but this does not resolve the issue. Only a hard reset consistently allows me to get the correct TDO results. Sequence being used (via my Python library executing TCL commands): open_device -hardware_name {USB-Blaster [USB-0]} -device_name {@1: JTAG_DEVICE (0x12345678)} device_lock -timeout 10000 device_ir_shift -ir_value 0x00000000 puts "TDO is: 0x[device_dr_shift -length 48 -value_in_hex]" device_unlock close_device Notes: - The Python library manages TCL sessions in a dedicated terminal. - I observe the same issue when performing these operations using Quartus directly. My question: Is there a Quartus or TCL command or procedure that can help avoid the need for a hard reset after each boundary scan operation? Or is there a way to reliably ensure the correct TDO value is returned every time without hard resetting the device? Thank you for your assistance.
EDA_MAINTAIN_DESIGN_HIERARCHY obsolete?
Hi Community, I'm using Quartus Pro 25.1.1 and for simulation need to enable EDA_MAINTAIN_DESIGN_HIERARCHY during eda netlist writing. I wasn't able to find it somewhere in the settings and setting it via global assignment in qsf leads to this: # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation" # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation" Does anyone know how to turn the hierarchy preservation on? Thanks in advance!
