Quartus Eda_Writer keeps crashing
Quartus Prime v25 keeps crashing at the eda_writer step during the flow on Windows 11. I have tried different Quartus versions (II v13.1, Prime Lite v25, Prime Standard v25). All of them crashed at this step multiple times. Is this an issue with the design that I am trying to implement? I searched for this error on Google and I found a message that said it was a bug that was fixed in version 21.1. Strange that its still occuring now in v25 standard. Problem Details Error: Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_hierarchy_builder.cpp, Line: 1097 m_bp_manager != NULL Stack Trace: 0x48eca: WSC_HIERARCHY_BUILDER::build_map_from_partitions + 0x8a (NETO_WSC) 0x46dd5: WSC_HIERARCHY_BUILDER::build_hierarchy_from_partitions + 0x35 (NETO_WSC) 0x45e1b: WSC_HIERARCHY_BUILDER::build + 0x22b (NETO_WSC) 0x16282: QNETO_START::build_hierarchy_netlist + 0x242 (quartus_eda) 0x28548: QNETO_START::generate_simulation_files + 0x688 (quartus_eda) 0x1a1e3: QNETO_START::generate_eda_files + 0x43 (quartus_eda) 0x33fd0: qneto_execute + 0x210 (quartus_eda) 0xa79b: QNETO_FRAMEWORK::execute + 0x26b (quartus_eda) 0x10b5f: qexe_do_normal + 0x22f (comp_qexe) 0x16fa0: qexe_run + 0x420 (comp_qexe) 0x18012: qexe_standard_main + 0xb2 (comp_qexe) 0x10d17: qneto_main + 0x77 (quartus_eda) 0x12208: msg_main_thread + 0x18 (CCL_MSG) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x11a41: msg_exe_main + 0xa1 (CCL_MSG) 0x36423: __scrt_common_main_seh + 0x10b (quartus_eda) 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) 0x8c53b: RtlUserThreadStart + 0x2b (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 25.1std.0 Build: 1129 Edition: Standard Edition
How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
Quartus Prime Pro 25.1 Crashes Randomly
I’ve been having trouble compiling projects with Quartus Prime Pro version 25.1 for several days. In an unpredictable manner, Quartus stops the compilation or freezes at a certain point—it can happen at the beginning, during synthesis, when the fitter starts, or during timing analysis. I’ve carried out extensive testing. I’ve tried reinstalling the program several times, and it’s true that right after installation, several successful compilations can be achieved; however, after around the fifth one, it usually starts failing and won’t compile anymore. The message window during compilation doesn’t provide any details about the error. I’ve also tried installing the newest version, but it behaves similarly. After a few attempts, I noticed that at the exact moment of the crash, the program generates a file called serv_req_info.txt, which I’ve attached. I’ve formatted my computer and updated to the latest version of Windows, and even replaced the internal SSD, but nothing has solved the issue. I’d appreciate any help in finding the cause of the problem.GTS SDI II IP Core not producing correct tx_vid_clkout frequency
I'm using an Agelix 5 (the Altera development board) with Quartus Pro 25.3.1 w/patch 1.02. i'm trying to set-up the GTS SDI II IP Core (version 2.3.0) on the Main screen, the only configurable values are: Video Standard = HD-SDI Direction = Transmitter Insert payload ID = off SDI_II wrapper = Both BASE and PHY everything else is grayed out. I have connected the tx_pll_refclk to the 148.5MHz input. I do see the tx_pll_locked signal behave as expected and it does lock. the problem is when I look at the tx_vid_clkout signal its 58.3MHz. I expected it to be 74.25MHz. I'm somewhat confused as to whether tx_pll_refclk should be 148.5MHz or 74.25MHz, but if the 148.5 is wrong then I would have expected tx_vid_clkout to be twice, not a somewhat random value of 58.3MHz. when I reconfigured the IP core for 3G-SDI, the tx_vid_clkout frequency doubled to 116MHz. The doubling would be what I expected, but still a wrong frequency. i'm not sure what i'm setting wrong and why i'm getting a clkout of 58.3MHzQuartus Assembler-only run after updating ROM .mif — should .sof/.pof checksum change?
Hello, I have a question about Quartus output files and checksums when only the Assembler is re-run. 1) Run a full compile once (Analysis & Synthesis + Fitter/Place & Route). 2) Modify a *.mif file that is used as the initialization file for a Quartus IP: “ROM: 1-PORT”. 3) Without re-running Analysis & Synthesis or the Fitter, run: 4) Processing → Start → Start Assembler 5) to regenerate the .sof and .pof files. A customer asked whether the checksum of the generated .sof/.pof should remain unchanged because the logic is not re-synthesized and the design is not re-fitted. However, in my repeated tests, the checksum of the .sof/.pof changes every time the contents of the .mif file change. Could you please confirm whether this behavior is expected? In other words, does the Assembler incorporate the updated memory initialization data into the programming files (thus changing the file contents/checksum), even though A&S and Fitter are not re-run? Any clarification or recommended flow for updating ROM init contents would be appreciated. Best regards,Question about building projects in Eclipse when migrating from Quartus 17.1 to 23.1
Hello, I am currently migrating my development environment to Windows 11 and trying to make an existing project created with Quartus 17.1 work in Quartus 23.1. Specifically, I have updated IP components, various settings, and both the FPGA-side and Nios-side programs to match the original project as closely as possible. File generation, compilation, and build processes all succeed, but when I programmed the FPGA, the behavior differed from the original project. After investigating, it seems that the issue may be related to the .hex or .elf files generated by Eclipse. For reference, Eclipse was included with Quartus 17.1, but it is not included in Quartus 23.1. Therefore, I set up Eclipse manually using WSL. Here are my questions: 1. I couldn’t use the existing project’s Makefile in Eclipse with Quartus 23.1, so I created a new one. Is there a way to build using the original Makefile? 2. Are there significant differences in how .hex or .elf files are generated when building in Eclipse with Quartus 17.1 versus 23.1? I would appreciate any guidance or advice.
