How-to generate dual-port (read/write) RAM with clock enables

Question

Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for

read/write clock mode
input/output clock mode

I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error:

Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family.

This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?

gerhardcadek · Answer

There is the same issue for Agilex 5. Again the documentation states:

Independent clock enables are supported in the following clocking modes:• Read/write clock mode—supported for both read and write clocks.• Input/output clock mode—supported for the registers of both ports

richardt_altera · Answer

You can use below setting to enable the wrclocken and rdoutclocken.- Use different clock enables for registers. (only available on Dual Clock: use separate "read" and "write" clocks)- Use clock enable for write input registers.- Use clock enable for output registers.
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Regards,Richard Tan

gerhardcadek · Answer

Hi Richard,thank you for this tipp. I will try this approach right next week!RegardsGerhard Cadek

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How-to generate dual-port (read/write) RAM with clock enables

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