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GerhardCadek's avatar
GerhardCadek
Icon for Occasional Contributor rankOccasional Contributor
9 months ago

How-to generate dual-port (read/write) RAM with clock enables

Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP g...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
8 months ago

Hi,

can you clarify the connection and implemented function of "existing dual-clock RAM with read clock enable"?

Regards
Frank