Synthesis error

I generated HDL file from qsys and did the compilation in Quartus. Following error log was found:

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of range [31:5] for 'addr'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_txctrl.sv(196): index 4 is out of range [1:0] for 'tx_data'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_txs.sv(196): index 95 is out of range [65:0] for 'rx_fifo_data'

Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_app.sv(597): index 257 is out of range [71:0] for 'rx_fifo_dataq'

Error(16851): Verilog HDL error at udh_en0.sv(127): formal port avs0 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at udh_en0.sv(125): formal port avs1 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at udh_en0.sv(123): formal port avs2 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at udh_en0.sv(122): formal port avs3 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at udh_en0.sv(121): formal port avm0 of type avlmm_ifc' from library 'function_enet_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at udh_en0.sv(119): formal port mdio_r of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at udh_en0.sv(120): formal port mdio_s of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at udh_en0.sv(118): formal port mdio_t of type mdio_ifc' from library 'function_enet_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at hssl_i.sv(130): formal port avs of type avlmm_ifc' from library 'function_hssl_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at hssl_i.sv(127): formal port avm0 of type avlmm_ifc' from library 'function_hssl_20 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at hssl_i.sv(128): formal port gmii_r of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at hssl_i.sv(129): formal port gmii_s of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at hssl_i.sv(131): formal port gmii_t of type gmii_ifc' from library 'function_hssl_20 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at hssl_i.sv(125): formal port mdio_r of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at hssl_i.sv(126): formal port mdio_s of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at hssl_i.sv(124): formal port mdio_t of type mdio_ifc' from library 'function_hssl_20 does not match with actual type mdio_ifc' from library 'altera_work

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(380): formal port gmii0 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(382): formal port gmii1 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(377): formal port gmii2 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(378): formal port gmii3 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(374): formal port gmii4 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(376): formal port gmii5 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(372): formal port gmii6 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(373): formal port gmii7 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(370): formal port gmii8 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(371): formal port gmii9 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(366): formal port gmii10 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(367): formal port gmii11 of type gmii_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type gmii_ifc' from library 'function_enet_20

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(391): formal port avs0 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(390): formal port avs1 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(387): formal port avs2 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(386): formal port avs3 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(389): formal port avs4 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(388): formal port avs5 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16851): Verilog HDL error at qsgmii2gmii_0.sv(383): formal port avs6 of type avlmm_ifc' from library 'QSGMII_to_GMII_Bridge_10 does not match with actual type avlmm_ifc' from library 'ast2avmm_pcie_bridge_hw_191

Error(16186): Can't elaborate top-level user hierarchy

Error: Flow failed:

Error: Quartus Prime Synthesis was unsuccessful. 65 errors, 191 warnings

Error: Peak virtual memory: 1041 megabytes

Error: Processing ended: Wed Sep 23 11:02:52 2026

Error: Elapsed time: 00:01:58

Error: System process ID: 23412

Error(293001): Quartus Prime Full Compilation was unsuccessful. 67 errors, 191 warnings





It seems the instantiated avlmm(for instance) is trying to map to the same module in altera_work which gneerates this error. How do i solve it?