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Vishnu_Ajith's avatar
Vishnu_Ajith
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20 days ago

Synthesis error

I generated HDL file from qsys and did the compilation in Quartus. Following error log was found: Error(13224): Verilog HDL or VHDL error at altpcieav_256_rp_rxm_rdwr.sv(287): index 3 is out of rang...
Compilation
Vishnu_Ajith's avatar
Vishnu_Ajith
Icon for New Contributor rankNew Contributor
20 days ago

sstrell​ Yes it does. Although some warnings were there it did generate. One more point to be added is the files were developed on 20.3 version and I am using 21.3. But I did see the synthesis report of previous compilation and it showed 21.3. Is the simulation version sensitive? 

ShengN_altera's avatar
ShengN_altera
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14 days ago

Hi

 

Any further update does your problem had been resolved?