About Single Event Upset (SEU)

The target devices are MAX 10, Cyclone 10 LP, Cyclone V, and Agilex 3.

I would like to confirm the details about SEU for these devices.

Question 1:

Please explain how the FIT value shown in the "Projected SEU FIT" report for a project in Quartus is calculated.

We are being asked, “What is the basis and condition under which this number is derived?”

Since our competitors provide this information, we would like Altera to present it as well.

I have the following publicly available documents, but since they do not mention any specific calculation formulas, we are making this inquiry.

https://docs.altera.com/r/docs/683869/current/an-866-mitigating-and-debugging-single-event-upsets-in-quartus-prime-standard-edition/quartus-prime-software-seu-fit-reports

Question 2:

Please provide information on the device structure and supporting data (numerical values) regarding SEU tolerance.

Since both AMD (Xilinx) and Lattice have disclosed such information, we would like Altera to present it as well.

Best Regards