platform

361 Topics

Remote Update IP Support for Generic Serial Flash Interface on Cyclone V?
Does the Remote Update IP for Cyclone V support the Generic Serial Flash Interface IP? I would like to request private message support. Thank you.
Praxis_Kernfeld
2 hours ago Place Quartus® Prime
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How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
wa_itd
6 days ago Place Quartus® Prime
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A5EG013BB18A OPN is visible in Quartus but not listed in Program File Generator
Hi everyone, I am currently working on programming an SCM FPGA board using Intel Quartus 25.1 . Our target FPGA OPN is A5EG013BB18A. I need to generate a .jic file from a .sof file by using the Program File Generator. However, when I try to select the FPGA Device in the Program File Generator, we cannot find A5EG013BB18A in the device list. The strange thing is that A5EG013BB18A can be seen in other places within Quartus, but it is not shown only in the Program File Generator device selection list. I have attached screenshots and related files showing: 1. The device can be seen in Quartus 2. The Program File Generator FPGA Device selection list 3. The content of .ini file and the .qsf file Could anyone help confirm the following? Is A5EG013BB18A supported in the Program File Generator? 2. Is there any specific .ini file setting or placement required for the Program File Generator to show this OPN? 3. Is a specific Quartus version or device package required? 4. Is there any known limitation where an OPN is visible in Quartus but not available in the Program File Generator? Any advice or reference would be appreciated. Thank you.
C_HWANG
15 days ago Place Quartus® Prime
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12Comments
NIOS-V Shell: qsys-generate not found
Hello, we are using makefiles to build our Quartus & QSYS projects. Since we switched from NIOS-II shell to NIOS-V shell, I realized that qsys-generate is no longer accesible. The command "qsys-generate.exe" is either misspelled or was not found. Other quartus commandline tools remain available in NIOS-V Shell: quartus_sh/quartus_sh.exe quartus_fit/quartus_fit.exe The command qsys-generate.exe does exist, it is simple not added to the path in NIOS-V shell. What is the correct way to invoke qsys-generate.exe from within NIOS-V shell? best regards Fabian
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FabianL
16 days ago Place Quartus® Prime
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Mailbox Client IP - SEND_CERTIFICATE command through FPGA fabric
Hi colleagues, under Agilex3C (A3CY135BM16A) Non-HPS with Quartus 26.1 (latest SDM, latest IPs) how one can send compact certificates to SDM through the internal FPGA fabric? I tried it with Mailbox Client (1024/1024 FIFO depth, AXI accelerator path disabled) + SPI slave/JTAG Avalon Master, all other SDM commands (incl. the complicated ones like SPI programming with larger payloads) are working fine except this one. The error I get back all the time is 0xF00000FF (which appears as 0x3FF in SDM level1 log), so generic error, no explanation. When I load the same certificate over JTAG (external JTAG not via JTAG Avalon bridge to Mailbox Client), then it is working fine (so signature and certificate content is right). I tried both burning fuse or just loading virtual fuse with/without test bit. All gives back this same answer if it has been sent over FPGA Fabric SDM mailbox. Does anyone know any example project for this? (I tried to make it work based on ATF-A mailbox driver's VAB certificate loading command implementation (which theoretically should accept other certificates too). I believe this is something supposed to work without HPS. (otherwise you should leave JTAG enabled in your system). Links: arm-trusted-firmware/plat/altera/soc/common/include/socfpga_mailbox.h at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware arm-trusted-firmware/plat/altera/soc/common/soc/socfpga_mailbox.c at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware Thanks, Peter
dpcsu_e
20 days ago Place Quartus® Prime
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How to create a new component that instantiates a IP variant in PD?
Hi, I want to connect an Avalon stream multiplexer to an Avalon S2MM Memory FIFO using a dual clock FIFO that has different input and output width. My data packet from the Avalon stream multiplexer is 128-bit and the S2MM Memory FIFO only supports 32-bit data when it is configured S2MM (I want to stream the data packet to HPS). Since the current Avalon stream FIFO dual clock does not support misaligned input and output width, I created a custom Avalon Stream DC FIFO the wraps a DCFIFO (128->32) IP. I wanted to use the Component Editor in Platform Designer to make the wrapped AVS DCFIFO an custom IP so I can instantiate it in Platform Designer. Here is my question, can I add the *.ip IP variant file along the HDL top-level file into the Component Editor file list to create the IP? If not, what are some alternate approaches to make instantiating HDL + IP comb in Platform designer happen? Thanks,
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YZhou98
1 month ago Place Quartus® Prime
176Views
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9Comments
The quartus license works with version 25.0 but not with version 17.0
Hello, I recently purchased a Quartus license. Unfortunately, it works with Quartus version 25.0, but not with version 17.0. Is there a solution for this? Thank you in advance Beroual
Beroual
1 month ago Place Quartus® Prime
195Views
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10Comments
Modifying and/or hiding interfaces based on component parameters?
I am working in Quartus Prime 26.1 with Platform Designer. I have created a _hw.tcl file for my new component. I would like to hide some interfaces based on the component parameters; for example, "Enable AXI-Stream Output" would un-hide an optional AXI-Stream interface. I have tried using an elaboration callback (described here), but Platform Designer complains upon loading the _hw.tcl file, stating that the "Component Editor does not save TCL callbacks", and asks me to remove the callback. I cannot replace ENABLE true with ENABLE [get_parameter_value ... ] either; this also causes an error. Any help would be greatly appreciated!
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wa_itd
1 month ago Place Quartus® Prime
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RTL Simulation fails with: couldn't execute ip-setup-simulation: invalid argument
Hi , Error: Failed to run ip-setup-simulation: couldn't execute "c:\altera_pro\26.1\quartus\..\vds\bin\ip-setup-simulation": invalid argument I have been facing this issue since morning, unable to run the simulation, yesterday it was working fine. Even tried regenerating IP files also today, but got the same error. Any help is appreciated. Regards, Sai@2403
Sai2403
1 month ago Place Quartus® Prime
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6Comments
How to specify the library for files in the Component Editor?
I am making a custom IP component in Quartus Prime 26.1. Most files are simply part of the "work" library, however there is at least one file which needs to be compiled under a specific library name. I have created my own _hw.tcl file, which is working fine. The problem is, that when I include all my files, I do not know how to specify the library each file should be compiled into. This results in an error message when synthesising: VHDL Use Clause at MyFile.vhd(29): design library "mylib" does not contain primary unit "mylibcomponents". It would seem natural that there'd be an attribute or something you can apply to a file or fileset, which would specify the library; however, I've been unable to find anything. Many thanks in advance for any guidance!
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wa_itd
1 month ago Place Quartus® Prime
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5Comments