Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[1]
Hello. Please, suggest how to resolve this error. Quartus 25.1, Cyclone V, Start Fitter. inout [3:0] HPS_DDR3_DQS_N, inout [3:0] HPS_DDR3_DQS_P, .memory_mem_dqs (HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n (HPS_DDR3_DQS_N), // .mem_dqs_n
Floating point operation on Cyclone 10 GX
Hello, I have a few questions regarding the way DSP resources are used in the FPGA I’m working with, a Cyclone 10 GX 10CX220YF780I5G. I want to perform an FMA (Fused Multiply-Add) operation using one of the available IPs in the catalog for floating-point operations, but I suspect that the one I’m currently using doesn’t execute the operation jointly as a + b * c; instead, it performs a + (b * c), which leads to errors due to intermediate rounding. The IP I’m using is Floating Point Functions FPGA IP, but there are others available that I believe might accomplish the same operation, such as Floating Point Hardware 2 Multi‑Cycle Intel FPGA or Native Floating Point DSP Cyclone 10 GX FPGA. I can’t find any information in the documentation about whether these operations are fused or not. Does anyone have any information on this? Thanks in advance.
Design Space Explorer - *** Fatal Error: Access Violation at 0X000000001E19EB30
I've used this Virtual PC many times in the past to run DSE, however, after about 1 year and re-trying to launch DSE Quartus crashes immidiately with the following error: Summarized as follows: full report attached below. Quartus Prime Problem Report Executable: quartus_dsew.exe Edition: Standard Edition Version: 18.1.1 Build: 646 Address bits: 64 Platform: Windows 10 64-bit VM: Error: *** Fatal Error: Access Violation at 0X000000001E19EB30 Module: quartus_dsew.exe Stack Trace (truncated for readability): PyModule_GetNameObject (python36) _PyCFunction_FastCallDict (python36) _Py_CheckFunctionResult (python36) _PyEval_EvalFrameDefault (python36) PyArg_UnpackTuple (python36) PyImport_ImportModuleLevelObject (python36) PyEval_EvalCode (python36) PyCFunction_Call (python36) _PyFunction_FastCallDict (python36) _PyObject_FastCallDict (python36) _PyObject_CallMethodIdObjArgs (python36) Full stack trace available in original Quartus crash dialog.
QSYS Subsystem Export Port order
Hello, I'm having a hierarchical QSYS System which uses other QSYS file as subsystem. My problem is, that I cannot find a way to reliable define the order of export Ports of the subsystem, i.e. the graphical order in which they appear in the instantiating top level. The Thread is somehow related to this: Ordering of Ports for exported Qsys signal conduits | Altera Community, but the solution proposed there does not work. System Information: Quartus Pro 25.3 Device Arria 10 What I have done so far to try to customize the order of export Ports: Remove all the export ports, save the .qsys subsystem and re-export the port in the correct order, as proposed in the above mentioned thread ==> no effect at all the export ports appeared in the top level in exact the same order as before Manually edit the XML file of the .qsys subsystem and rearrange the listed ports in the desired order. ==> no effect at all the export ports appeared in the top level in exact the same order as before Remove the driving IP core for all export ports and readd the IP cores in the desired order of their export ports ==> This actually had an effect, but this basically means rewriting the whole QSYS subsystem which is not an option. After all of the above mentioned steps, I execute a "Refresh System and Reload all Components". Am I missing something? What is the officially recommended way by Altera to define the order of export Ports of a QSYS Subsystem. NOTE: This only corresponds to QSYS subsystem. It is not a problem with custom IP files based on any HDL I'm thankful for any advice. best regards Fabian
How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
Arria10 Platform Designer EMIF
Hi I am using platform designer with the Arria10. I have two DDR3 memory interfaces which use clock sharing so they should share the same clock domain. Platform designer inserts clock crossing logic when accessing the memory interface I do not source the system clock from. Is there anyway to prevent this? Regards, GraemeCDC Interconnect in Platform Designer
Hello community, I have several custom DSP blocks that expose an AXI4-Lite CSR interface for system control and monitoring. These registers need to be accessed from the HPS (bare-metal/Yocto) via the H2F lightweight AXI bridge. The H2F LW bridge operates on a 100 MHz clock, while the AXI4-Lite interfaces inside the DSP blocks are synchronous to a separate DSP clock that is asynchronous to the 100 MHz domain. I am currently using the Intel AXI interconnect in Platform Designer to connect the LW bridge to the DSP blocks, and I’ve observed that No clock-domain crossing logic is being inserted between the LW bridge and the DSP AXI interfaces. My question is: does Platform Designer provide an interconnect mechanism (similar to Xilinx AXI interconnects) that allows connecting AXI master and slave interfaces in different clock domains and automatically handles the required CDC logic? Or is explicit CDC handling required at the AXI slave interface level for this use case? Any guidance or best practices would be greatly appreciated.
