platform

361 Topics

How to create a Packaged Subsystem in TCL
I am hoping to create a script which will automatically package the IP I am working on as a packaged subsystem. So far, I have automated the creation of an IP directory which describes a new component using a _hw.tcl file and the various source files. I believe the next step is to take this component, instantiate it in a Platform Designer system, and create a Packaged Subsystem using it. I am also hoping that I can parameterise and hide/modify ports of the packaged subsystem, like I can with the _hw.tcl component description. I am encountering a problem; I am running the following command: qsys-script --script=create_packaged_subsystem.tcl --new-quartus-project=my_project_name However, the script fails for the following reason: Error: invalid command name "set_package_property" Here is the script itself (more or less a copy-and-paste from the GUI): package require -exact qsys 26.1 set_package_property NAME "packagename" set_package_property DISPLAY_NAME "PackageName" set_package_property VERSION "1.0" set_package_property GROUP "GroupName" set_package_property DESCRIPTION "A descripton." set_package_property ELABORATION_CALLBACK elaboration_callback set_package_property EXTRACTION_CALLBACK extraction_callback add_fileset synth_fileset QUARTUS_SYNTH fileset_callback "Quartus Synthesis Fileset" add_fileset sim_verilog_fileset SIM_VERILOG fileset_callback "Simulation Verilog Fileset" proc elaboration_callback {} { enable_all_instances } proc extraction_callback {} { extract_modules } proc fileset_callback { output_name } { generate_all_instances } Any help would be hugely appreciated, on this issue and on my general workflow. Also if it is possible to encrypt packaged subsystems or components using Quartus I'd be keen to know. Thanks!
wa_itd
8 hours ago Place Quartus® Prime
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Modifying and/or hiding interfaces based on component parameters?
I am working in Quartus Prime 26.1 with Platform Designer. I have created a _hw.tcl file for my new component. I would like to hide some interfaces based on the component parameters; for example, "Enable AXI-Stream Output" would un-hide an optional AXI-Stream interface. I have tried using an elaboration callback (described here), but Platform Designer complains upon loading the _hw.tcl file, stating that the "Component Editor does not save TCL callbacks", and asks me to remove the callback. I cannot replace ENABLE true with ENABLE [get_parameter_value ... ] either; this also causes an error. Any help would be greatly appreciated!
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wa_itd
1 day ago Place Quartus® Prime
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How to create a new component that instantiates a IP variant in PD?
Hi, I want to connect an Avalon stream multiplexer to an Avalon S2MM Memory FIFO using a dual clock FIFO that has different input and output width. My data packet from the Avalon stream multiplexer is 128-bit and the S2MM Memory FIFO only supports 32-bit data when it is configured S2MM (I want to stream the data packet to HPS). Since the current Avalon stream FIFO dual clock does not support misaligned input and output width, I created a custom Avalon Stream DC FIFO the wraps a DCFIFO (128->32) IP. I wanted to use the Component Editor in Platform Designer to make the wrapped AVS DCFIFO an custom IP so I can instantiate it in Platform Designer. Here is my question, can I add the *.ip IP variant file along the HDL top-level file into the Component Editor file list to create the IP? If not, what are some alternate approaches to make instantiating HDL + IP comb in Platform designer happen? Thanks,
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YZhou98
1 day ago Place Quartus® Prime
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A5EG013BB18A OPN is visible in Quartus but not listed in Program File Generator
Hi everyone, I am currently working on programming an SCM FPGA board using Intel Quartus 25.1 . Our target FPGA OPN is A5EG013BB18A. I need to generate a .jic file from a .sof file by using the Program File Generator. However, when I try to select the FPGA Device in the Program File Generator, we cannot find A5EG013BB18A in the device list. The strange thing is that A5EG013BB18A can be seen in other places within Quartus, but it is not shown only in the Program File Generator device selection list. I have attached screenshots and related files showing: 1. The device can be seen in Quartus 2. The Program File Generator FPGA Device selection list 3. The content of .ini file and the .qsf file Could anyone help confirm the following? Is A5EG013BB18A supported in the Program File Generator? 2. Is there any specific .ini file setting or placement required for the Program File Generator to show this OPN? 3. Is a specific Quartus version or device package required? 4. Is there any known limitation where an OPN is visible in Quartus but not available in the Program File Generator? Any advice or reference would be appreciated. Thank you.
C_HWANG
1 day ago Place Quartus® Prime
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Mailbox Client IP - SEND_CERTIFICATE command through FPGA fabric
Hi colleagues, under Agilex3C (A3CY135BM16A) Non-HPS with Quartus 26.1 (latest SDM, latest IPs) how one can send compact certificates to SDM through the internal FPGA fabric? I tried it with Mailbox Client (1024/1024 FIFO depth, AXI accelerator path disabled) + SPI slave/JTAG Avalon Master, all other SDM commands (incl. the complicated ones like SPI programming with larger payloads) are working fine except this one. The error I get back all the time is 0xF00000FF (which appears as 0x3FF in SDM level1 log), so generic error, no explanation. When I load the same certificate over JTAG (external JTAG not via JTAG Avalon bridge to Mailbox Client), then it is working fine (so signature and certificate content is right). I tried both burning fuse or just loading virtual fuse with/without test bit. All gives back this same answer if it has been sent over FPGA Fabric SDM mailbox. Does anyone know any example project for this? (I tried to make it work based on ATF-A mailbox driver's VAB certificate loading command implementation (which theoretically should accept other certificates too). I believe this is something supposed to work without HPS. (otherwise you should leave JTAG enabled in your system). Links: arm-trusted-firmware/plat/altera/soc/common/include/socfpga_mailbox.h at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware arm-trusted-firmware/plat/altera/soc/common/soc/socfpga_mailbox.c at socfpga_v2.14.0 · altera-fpga/arm-trusted-firmware Thanks, Peter
dpcsu_e
2 days ago Place Quartus® Prime
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RTL Simulation fails with: couldn't execute ip-setup-simulation: invalid argument
Hi , Error: Failed to run ip-setup-simulation: couldn't execute "c:\altera_pro\26.1\quartus\..\vds\bin\ip-setup-simulation": invalid argument I have been facing this issue since morning, unable to run the simulation, yesterday it was working fine. Even tried regenerating IP files also today, but got the same error. Any help is appreciated. Regards, Sai@2403
Sai2403
7 days ago Place Quartus® Prime
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How to specify the library for files in the Component Editor?
I am making a custom IP component in Quartus Prime 26.1. Most files are simply part of the "work" library, however there is at least one file which needs to be compiled under a specific library name. I have created my own _hw.tcl file, which is working fine. The problem is, that when I include all my files, I do not know how to specify the library each file should be compiled into. This results in an error message when synthesising: VHDL Use Clause at MyFile.vhd(29): design library "mylib" does not contain primary unit "mylibcomponents". It would seem natural that there'd be an attribute or something you can apply to a file or fileset, which would specify the library; however, I've been unable to find anything. Many thanks in advance for any guidance!
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wa_itd
8 days ago Place Quartus® Prime
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ES vs Production SOF
Hi, I am encountering this error: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0x4364F0DD for device 1, but found JTAG ID code 0x0364F0DD. The SOF was built on the ES family, matching the Altera silicon we have. Yet Quartus System-Console 26.1 throws an error and refuses to load the SOF on the device. Can this input validation be disabled, and the SOF be forced loaded in System Console? Is this a JTAG ID readback issue from the Altera silicon, or is this an SOF decoding issue? the error message is not clear. May 05, 2026 11:06:33 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Executing startup script C:\altera_pro\26.1\qprogrammer\quartus\..\syscon\scripts\system_console_rc.tcl May 05, 2026 11:06:33 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: The script doesn't exist: C:\Users\myuser\system_console\system_console_rc.tcl. You can customize System Console by creating one. May 05, 2026 11:06:33 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Executing startup script C:\<somewhere>\tcp_silent.tcl Start the server on port 2540 Port 2540 is free Binding server to port 2540 ... Server is listening on port 2540 Wait for clients. To connect, open a terminal and type: "telnet 127.0.0.1 2540" Example commands to try: [*] get_service_types [*] get_service_paths {device} % Accept sock3868 from 127.0.0.1 port 50523 Handle the client via a fileevent callback Info (19848): Regular SEU info => 9 sector(s), 9 thread(s), 10000000 interval time in microsecond(s) Info (19848): IO hash is 3F5AB0523916653E0C52DCBFFC9552316FE01528E94CA6CDF645360951BDA1D4 Info (19848): Keyed hash is 9CFF525F61EA326BDA5433320977E6E4470F4EDC9CC061CBB9B86CE95FDD5D69 Info (19848): Design hash is C8624ABCFA89155074C0CC0C070ADA6EC3CD3A32E659C8490E1283347F543E3F Info (19848): IO hash is 3F5AB0523916653E0C52DCBFFC9552316FE01528E94CA6CDF645360951BDA1D4 Info (19848): Keyed hash is 09AF25D3F828210F8E68472EBAEA0E3866E0F2195EDFB0FD18AF5C5AB6193C85 Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Command: quartus_pgm --no_banner --mode=jtag --cable="Arrow-USB-Blaster on localhost [ARA39943-TEI0004]" --operation="p;C:\<somewhere>\FantasticBits_1_1_1_0x66EA5AFB.sof@1" Info (213045): Using programming cable "Arrow-USB-Blaster [ARA39943-TEI0004]" Info (213011): Using programming file C:/<somewhere>/FantasticBits_1_1_1_0x66EA5AFB.sof with checksum 0x1F8E0B47 for device A5EC065BB32A@1 Info (209060): Started Programmer operation at Tue May 5 11:07:12 2026 Info (18942): Configuring device index 1 Error (18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0x4364F0DD for device 1, but found JTAG ID code 0x0364F0DD. Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue May 5 11:07:12 2026 Error: Quartus Prime Programmer was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 786 megabytes Error: Processing ended: Tue May 5 11:07:12 2026 Error: Elapsed time: 00:00:21 Error: System process ID: 57136 May 05, 2026 11:07:12 AM com.altera.systemconsole.scripting.TCLCommand execute2 SEVERE: device_download_sof: Unable to load the sof: C:\<somewhere>\FantasticBits_1_1_1_0x66EA5AFB.sof May 05, 2026 11:07:13 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering JTAG connections May 05, 2026 11:07:18 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering USB connections Info (19848): Regular SEU info => 9 sector(s), 9 thread(s), 10000000 interval time in microsecond(s) Info (19848): IO hash is 3F5AB0523916653E0C52DCBFFC9552316FE01528E94CA6CDF645360951BDA1D4 Info (19848): Keyed hash is 9CFF525F61EA326BDA5433320977E6E4470F4EDC9CC061CBB9B86CE95FDD5D69 Info (19848): Design hash is C8624ABCFA89155074C0CC0C070ADA6EC3CD3A32E659C8490E1283347F543E3F Info (19848): IO hash is 3F5AB0523916653E0C52DCBFFC9552316FE01528E94CA6CDF645360951BDA1D4 Info (19848): Keyed hash is 09AF25D3F828210F8E68472EBAEA0E3866E0F2195EDFB0FD18AF5C5AB6193C85 Info: ******************************************************************* Info: Running Quartus Prime Programmer Info: Command: quartus_pgm --no_banner --mode=jtag --cable="Arrow-USB-Blaster on localhost [ARA39943-TEI0004]" --operation="p;C:\<somewhere>\FantasticBits_1_1_1_0x66EA5AFB.sof@1" Info (213045): Using programming cable "Arrow-USB-Blaster [ARA39943-TEI0004]" Info (213011): Using programming file C:/<somewhere>/FantasticBits_1_1_1_0x66EA5AFB.sof with checksum 0x1F8E0B47 for device A5EC065BB32A@1 Info (209060): Started Programmer operation at Tue May 5 11:07:33 2026 Info (18942): Configuring device index 1 Error (18952): Error status: The device chain in Programmer does not match physical device chain. Expected JTAG ID code 0x4364F0DD for device 1, but found JTAG ID code 0x0364F0DD. Error (209012): Operation failed Info (209061): Ended Programmer operation at Tue May 5 11:07:33 2026 Error: Quartus Prime Programmer was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 786 megabytes Error: Processing ended: Tue May 5 11:07:33 2026 Error: Elapsed time: 00:00:21 Error: System process ID: 45680 May 05, 2026 11:07:33 AM com.altera.systemconsole.scripting.TCLCommand execute2 SEVERE: device_download_sof: Unable to load the sof: C:\<somewhere>\FantasticBits_1_1_1_0x66EA5AFB.sof May 05, 2026 11:07:39 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering JTAG connections May 05, 2026 11:07:39 AM com.altera.systemconsole.internal.core.SystemConsole logInfo INFO: Finished discovering USB connections
covfefe
9 days ago Place Quartus® Prime
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Agilex3 dcio parsing issue with RSU
Dear support, I am facing with the following issue: Environment: Quartus prime pro 26.1.0 build 110 (03/26/2026) on windows 11 Target board: Agilex3C evaluation kit (non-hps) Cosigned SDM + Authentication enabled Quartus pfg config file attached (manual.pfg.txt) I can successfully program the flash (the rbf helper signed) via Quartus programmer so the generated jic image is there. When I power-cycle the board and check in configuration debugger the RSU status, I get the following picture: attached rsu_dcio_issue.png I tried to generate the boot.rbf: from sof with -o rsu_boot=ON without injecting sdm without signing the rbf from sof with -o rsu_boot=ON with injecting a signed sdm, with signing the rbf (and basically all the combination with/without signing) In all cases I get back this same issue. QSF file also attached. I validated if I can load from configuration debugger the 1) Factory image (entered base address) --> OK 2) P1 image --> OK 3) P2 image --> OK so it looks like the error is either in the tables or in the decision firmware image itself. The decision firmware.rbf image I signed with permission 0x6, the agilex3.zip with permission 0x1 Today I basically iterated through all the possible way and it still fails. If anyone has any idea where to debug it further (online help again not helping too much), please let me know. Since the issue happening at commands those were in the normal and security guideline and where there are not so much parameters I believe it is either: 1) qsf issue, i am missing some assignment or have false setting --> but which one?? 2) quartus sw issue One last thing: Permission for signing SDM was 0x1 Permission for signing BOOT_INFO / FACTORY_IMAGE / User partitions were 0x6 quartus_sign did not allow me to sign BOOT_INFO with 0x1 permission Signing chains: root0 -> 2x QKY: firmware signing key (0x1) + design signing key (0x6) Update: Is this related to the following entry?! Error(22650): File <filename>.jic is corrupted. DCIO/Main section data information is not found | Altera Community - 351710 Update2: After disabling in the .pfg file the factory fallback: <partition reserved="1" fixed_s_addr="1" s_addr="0x00000000" factory_fallback="0" e_addr="0x0020FFFF" fixed_e_addr="1" id="BOOT_INFO" size="0"/> the issue did not happen anymore --> confirming the issue in 351710 still exists with Quartus 26.1 Thank you for your help in advance! Kind regards, Peter
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dpcsu_e
16 days ago Place Quartus® Prime
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Interfacing Avalon Streaming FIFO IP with GTS Ethernet Hard IP
Hello, I want to integrate the Avalon Streaming Single Clock FIFO IP (AVST FIFO IP) with the GTS Ethernet Hard IP (GTS EHIP) , but the GTS EHIP outputs signals rxstatus_valid and rxstatus_data, that don't interface with the AVST FIFO IP. The AVST FIFO IP is in a custom module in between the GTS EHIP and the rest of the 1x10G Ethernet System Example Design: Agilex 5 FPGA E-Series Modular Development Kit (Link: https://altera-fpga.github.io/rel-25.3/embedded-designs/agilex-5/e-series/modular/ethernet/agx5e-ethernet-10g/ug-agx5e-ethernet-10g/). How should I handle these signals? Can I ignore them? Is there a example reference design that does this? Thank you for the help! IP Blocks: AVST FIFO Parameters:
opexsys
27 days ago Place Quartus® Prime
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