Agilex 5 – Critical HSSI Error in JESD204B Example Design
Hi, I am bringing up the JESD204B interface on the dev kit. For this, I used the "Generate Example Design" option with the following parameters: When I generate the project and start synthesis, it reaches the "HSSI Support Logic Generation" stage, and Quartus reports the following critical error: It turns out that the generated file contains an inconsistency in the generated HSSI metadata. My fix was to replace the entry in: The problem is that after updating the Qsys file, it gets changed back to intel_jesd_RX, and HSSI reports the critical error again. If there is already a fix or workaround for this issue, please let me know. For now, I added a simple script that I run from PowerShell: that replaces this value with the correct one:Two different build merges as one
I am working on a project to combine two FPGAs into one. One FPGA design is by an external vendor. The vendor cannot provide project source files except pinouts. Their design has NIOS and SDK embedded software. Both of us are using the same FPGA. Resource-wise, both designs can be combined into one FPGA of the same part number. My design is using HPS. Both the HPS and NIOS need to communicate. Altera Pro allows NIOS and HPS connected via AXI bus in Platform Designer. All examples are showing within one Qsys file how to do this. But here we have two different projects. Is it possible to incorporate their project output files into my project and build an image? What file types and format I should ask the other vendor to provide? How do you merge the design within Altera Pro Ed build environment (GUI or through script)?USB-BlasterII mounts as "USB-Blaster variant"
Hello! My company uses the USB-BlasterII pods with Quartus. Many times, when the Blaster is plugged in, it is detected by Quartus as "USB-Blaster variant" instead of "USB-BlasterII". When this happens, the JTAG clock frequency is not settable, and the pod will not operate correctly. The problem occurs equally with Quartus Prime 16.1 and Quartus Standard 24.1. I have not tried other versions of Quartus. This appears to be the same root issue that AdamLevine experienced in a previous Altera forum post: USB Blaster II | Altera Community. To answer the questions he was asked, Yes, we experience this issue on all the PCs we have tried the USB-BlasterII on. My company is running Windows 11. We tried numerous boards, but similar to Adam, the problem occurs whether a board is connected to the Blaster or not. The issue appears to be with the driver for the Blaster and how it is detected when it is connected to the PC. This problem has been occurring more lately than it used to, but we have had significant failure rates with this for the past two years almost. I know our JTAG pin connections are correct because the USB-BlasterII works perfectly IF AND ONLY IF it is detected with the correct device name but cannot work at all if it shows up with the wrong name in Quartus. Our conclusion is that the drivers for the USB-BlasterII have a problem. I suspect that the driver caches the Blaster devices that have been connected and encounters an error if the cache is not cleared by ejecting all the Blaster devices. Just a guess. Has anyone found the issues with the drivers? Is anyone from Intel available to look into this behavior? If not, would Intel supply my corporation with the driver source code so our engineers can fix it? Thanks!
Quartus Dark Theme on Linux - Solution
I have a solution for setting up a dark theme for Quartus Prime 25 on Linux (Mint) and setup a Github repo. The program modifies the stylesheet using a Rust program. https://github.com/saturn77/quartus-dark-linux This repo allows running Altera Quartus on Linux with a dark theme, providing a modern look while being easy on the eyes for Linux users. There are some dark stylesheets for Windows, but those simply will not work on Linux. Quartus's argument parser intercepts -stylesheet before Qt can process it on Linux. This project uses a small Rust LD_PRELOAD library to hook QApplication::exec() and inject the stylesheet directly via Qt's setStyleSheet() API. Tested with Quartus Prime Pro 25.3.1 (Qt 6.5.7) on Linux Mint 22.3 Cinnamon.
Error (169008): Can't turn on open-drain option for differential I/O pin HPS_DDR3_DQS_N[1]
Hello. Please, suggest how to resolve this error. Quartus 25.1, Cyclone V, Start Fitter. inout [3:0] HPS_DDR3_DQS_N, inout [3:0] HPS_DDR3_DQS_P, .memory_mem_dqs (HPS_DDR3_DQS_P), // .mem_dqs .memory_mem_dqs_n (HPS_DDR3_DQS_N), // .mem_dqs_n
Design Space Explorer - *** Fatal Error: Access Violation at 0X000000001E19EB30
I've used this Virtual PC many times in the past to run DSE, however, after about 1 year and re-trying to launch DSE Quartus crashes immidiately with the following error: Summarized as follows: full report attached below. Quartus Prime Problem Report Executable: quartus_dsew.exe Edition: Standard Edition Version: 18.1.1 Build: 646 Address bits: 64 Platform: Windows 10 64-bit VM: Error: *** Fatal Error: Access Violation at 0X000000001E19EB30 Module: quartus_dsew.exe Stack Trace (truncated for readability): PyModule_GetNameObject (python36) _PyCFunction_FastCallDict (python36) _Py_CheckFunctionResult (python36) _PyEval_EvalFrameDefault (python36) PyArg_UnpackTuple (python36) PyImport_ImportModuleLevelObject (python36) PyEval_EvalCode (python36) PyCFunction_Call (python36) _PyFunction_FastCallDict (python36) _PyObject_FastCallDict (python36) _PyObject_CallMethodIdObjArgs (python36) Full stack trace available in original Quartus crash dialog.
Floating point operation on Cyclone 10 GX
Hello, I have a few questions regarding the way DSP resources are used in the FPGA I’m working with, a Cyclone 10 GX 10CX220YF780I5G. I want to perform an FMA (Fused Multiply-Add) operation using one of the available IPs in the catalog for floating-point operations, but I suspect that the one I’m currently using doesn’t execute the operation jointly as a + b * c; instead, it performs a + (b * c), which leads to errors due to intermediate rounding. The IP I’m using is Floating Point Functions FPGA IP, but there are others available that I believe might accomplish the same operation, such as Floating Point Hardware 2 Multi‑Cycle Intel FPGA or Native Floating Point DSP Cyclone 10 GX FPGA. I can’t find any information in the documentation about whether these operations are fused or not. Does anyone have any information on this? Thanks in advance.
QSYS Subsystem Export Port order
Hello, I'm having a hierarchical QSYS System which uses other QSYS file as subsystem. My problem is, that I cannot find a way to reliable define the order of export Ports of the subsystem, i.e. the graphical order in which they appear in the instantiating top level. The Thread is somehow related to this: Ordering of Ports for exported Qsys signal conduits | Altera Community, but the solution proposed there does not work. System Information: Quartus Pro 25.3 Device Arria 10 What I have done so far to try to customize the order of export Ports: Remove all the export ports, save the .qsys subsystem and re-export the port in the correct order, as proposed in the above mentioned thread ==> no effect at all the export ports appeared in the top level in exact the same order as before Manually edit the XML file of the .qsys subsystem and rearrange the listed ports in the desired order. ==> no effect at all the export ports appeared in the top level in exact the same order as before Remove the driving IP core for all export ports and readd the IP cores in the desired order of their export ports ==> This actually had an effect, but this basically means rewriting the whole QSYS subsystem which is not an option. After all of the above mentioned steps, I execute a "Refresh System and Reload all Components". Am I missing something? What is the officially recommended way by Altera to define the order of export Ports of a QSYS Subsystem. NOTE: This only corresponds to QSYS subsystem. It is not a problem with custom IP files based on any HDL I'm thankful for any advice. best regards Fabian
How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
