Is there a specific driver for the USB Blaster III?
Is there a specific Linux driver or firmware which is required for the USB Blaster III (ArrowAXE5000)? It does not get detected when I run jtagconfig? # dmesg |grep 'USB Blaster III' -A1 [9415753.839630] usb 1-4.4: Product: USB Blaster III [9415753.839635] usb 1-4.4: Manufacturer: Altera # jtagconfig --version jtagconfig Version 25.1.0 Build 129 03/26/2025 SC Pro Edition Copyright (C) 2025 Altera Corporation. All rights reserved. # jtagconfig --enum No JTAG hardware available Does it require some specific firmware and software to load it?
How to create a new component that instantiates a IP variant in PD?
Hi, I want to connect an Avalon stream multiplexer to an Avalon S2MM Memory FIFO using a dual clock FIFO that has different input and output width. My data packet from the Avalon stream multiplexer is 128-bit and the S2MM Memory FIFO only supports 32-bit data when it is configured S2MM (I want to stream the data packet to HPS). Since the current Avalon stream FIFO dual clock does not support misaligned input and output width, I created a custom Avalon Stream DC FIFO the wraps a DCFIFO (128->32) IP. I wanted to use the Component Editor in Platform Designer to make the wrapped AVS DCFIFO an custom IP so I can instantiate it in Platform Designer. Here is my question, can I add the *.ip IP variant file along the HDL top-level file into the Component Editor file list to create the IP? If not, what are some alternate approaches to make instantiating HDL + IP comb in Platform designer happen? Thanks,
How-to generate dual-port (read/write) RAM with clock enables
Following Stratix® 10 Embedded Memory User Guide (2025.07.24) chapter 2.11.6 independent clock enables are supported for read/write clock mode input/output clock mode I start a "RAM 2-port" IP generation. I select "one read/write port" in the general tab and "dual clock use separate read and write clock" in the "Clks/Rd,Byte En" tab. Now I enable the clock enables in the "Reg/Clkens/Aclrs" tab "use clock for read input register" as well as same for "output registers". IP Parameter window immediuately shows an error: Error: testram.ram_2port_0: Clock enable for read input registers is unavailable while using 'Dual clock: use separate read and write clocks' for Stratix 10 device family. This is verified with Quartus Pro 18.1 and 25.3. Is this a bug of the software or the documentation?
QSYS Subsystem Export Port order
Hello, I'm having a hierarchical QSYS System which uses other QSYS file as subsystem. My problem is, that I cannot find a way to reliable define the order of export Ports of the subsystem, i.e. the graphical order in which they appear in the instantiating top level. The Thread is somehow related to this: Ordering of Ports for exported Qsys signal conduits | Altera Community, but the solution proposed there does not work. System Information: Quartus Pro 25.3 Device Arria 10 What I have done so far to try to customize the order of export Ports: Remove all the export ports, save the .qsys subsystem and re-export the port in the correct order, as proposed in the above mentioned thread ==> no effect at all the export ports appeared in the top level in exact the same order as before Manually edit the XML file of the .qsys subsystem and rearrange the listed ports in the desired order. ==> no effect at all the export ports appeared in the top level in exact the same order as before Remove the driving IP core for all export ports and readd the IP cores in the desired order of their export ports ==> This actually had an effect, but this basically means rewriting the whole QSYS subsystem which is not an option. After all of the above mentioned steps, I execute a "Refresh System and Reload all Components". Am I missing something? What is the officially recommended way by Altera to define the order of export Ports of a QSYS Subsystem. NOTE: This only corresponds to QSYS subsystem. It is not a problem with custom IP files based on any HDL I'm thankful for any advice. best regards Fabian
How to upgrade IP from Quartus 24.1 and add it to a Quartus 25.1 Project?
Hello ALTERA Quarts Experts, I have created and configured an ALT_PLL IP in Quartus Standard edition 24.1. Now i need to add that IP to a Quartus 25.1 Standard Edition project. I have tried this so far: added the IPs output files to my 25.1 project: readout_pll.qip, readout_pll.v, readout_pll_bb.v There is also a file called: readout_pll.ppf which appears to be an xml file. Not exactly sure what this is meant to do or if i also needed to add that? I then see the message from Quartus 25.1 asking me to do an auto IP upgrade, which id did and it was successful according to Quartus. But then i don't see the IP appear in the projects IP Catalogue even after i do an IP library refresh. Can anybody please tell me what else i need to do in order to be able to use the IP in my 25.1 Project ? I am having to do all this because the ALT_PLL symbol is all messed up and is unusable in Quartus Standard Edition 25.1. For That problem i have already created another post recently and have been assured this will be fixed. But for now until its fixed i need to do this IP upgrade. Thanks, BarryThe best way to implement SignalTapII
Hello Altera SigalTap Experts, I have been trying to use Signal Tap in my MAX10 FPGA with Quartus STD 25.1 project. I was trying to use the Signal Tap GUI at first. The problem seems to be that for the signals i want to add to my Signal Tap probes, even after i add a constraint such as: (* keep = "true" *) logic vio_init_source; for example in System Verilog on ALL the signals i want to see in Signal Tap, they keep getting synthesised away. So i don't see a lot of the signals i need post synthesis / post fitting. If i do a node search for them they either don't appear after the search OR if they appear and i try to add them to my Signal Tap probes list they appear in RED {meaning Signal Tap can't use them i guess}. Then you seem to be forced into doing a 'Rapid Recompilation' which in my experience always means that i need to do a full FPGA compilation. This seems a bit crazy when i already did a full FPGA compile to get to this stage in the first place and i did it with all my 'keep' constraints applied to all the signals i wanted to use with Signal Tap. I have also tried using the Signal Tap Instantiation in my RTL, but that method also has the same sort of problems. My Question is: what is the best method(s) to use to guarantee that Signal Tap can find my signals after doing a Synthesis and Fitting run ? The other question is that it seems (unlike with AMD/Xilinx VivadoScope) that every time i make a change to my trigger equation, signa tap needs to do a full recompile. This is surely wrong and a bit crazy too ! Signal Tap already knows all the signals i am using for my trigger logic so why does it need to do a full FPGA compile { or 'Rapid Recompilation' in Signal Tap speak } when i just change the trigger function ? Is there a better way to use Signal Tap to prevent this sort of behaviour ? Thanks for your help, Dr Barry HQSYS 25.3pro failed to generate VHDL simulation files for altera_remote_update_core
Hello, If I use altera_remote_update_core in a QSYS project using Quartus Version 25.3pro, the IP Generation fails with the following error message Info: sib_flash_subsys_remote_update_0: "Generating: altera_remote_update_core" Error: invalid command name "else" Info: while executing Info: "else { Info: do_vhdl_sim_cbx altera_remote_update_core Info: }" Info: (procedure "do_vhdl_sim" line 8) Info: invoked from within Info: "do_vhdl_sim altera_remote_update_core" Error: Generation stopped, 1 or more modules remaining Despite the error message being not very meaningful, I realized, that this fails only, when I select Simulation Model "VHDL". If I select simulation model "none" or "verilog" IP Generation works fine. The error is reproduceable by a simple QSYS project, which only contains altera_remote_update IP core. The error only occurs in Quartus 25.3pro. Using the exactly same project with Quartus 24.1pro works without error. Please advice, I would appreciate any help on this topic. Thanks best regards Fabian
Problem with wire level expressions in platform designer quartus pro 25.1
I have a platform designer system which uses wire level expression original produced using quartus pro 20.4. For a new project I am using this system with quartus 25.1. When opening the system platform designer reports that any component with a wire level expression endpoint is out of date. Upgrading the component does not resolve the issue, the only way to fix the issue is to remove the wire level expressions. Has wire level expression support changed in newer quartus versions and is there a way to work around this? Kind regards Graeme
