USB-BlasterII mounts as "USB-Blaster variant"
Hello! My company uses the USB-BlasterII pods with Quartus. Many times, when the Blaster is plugged in, it is detected by Quartus as "USB-Blaster variant" instead of "USB-BlasterII". When this happens, the JTAG clock frequency is not settable, and the pod will not operate correctly. The problem occurs equally with Quartus Prime 16.1 and Quartus Standard 24.1. I have not tried other versions of Quartus. This appears to be the same root issue that AdamLevine experienced in a previous Altera forum post: USB Blaster II | Altera Community. To answer the questions he was asked, Yes, we experience this issue on all the PCs we have tried the USB-BlasterII on. My company is running Windows 11. We tried numerous boards, but similar to Adam, the problem occurs whether a board is connected to the Blaster or not. The issue appears to be with the driver for the Blaster and how it is detected when it is connected to the PC. This problem has been occurring more lately than it used to, but we have had significant failure rates with this for the past two years almost. I know our JTAG pin connections are correct because the USB-BlasterII works perfectly IF AND ONLY IF it is detected with the correct device name but cannot work at all if it shows up with the wrong name in Quartus. Our conclusion is that the drivers for the USB-BlasterII have a problem. I suspect that the driver caches the Blaster devices that have been connected and encounters an error if the cache is not cleared by ejecting all the Blaster devices. Just a guess. Has anyone found the issues with the drivers? Is anyone from Intel available to look into this behavior? If not, would Intel supply my corporation with the driver source code so our engineers can fix it? Thanks!
I am looking for a version of Quartus that meets the requirements.
I am looking for Quartus that meets the following conditions. ・It is compatible with Cyclone V. ・Windows 11 is included in the supported operating systems. I couldn't find it in the release notes, so I'm asking. I am waiting for your response.
Platform designer/NiosII Eclipse: SRAM controller error
Dear all, Good day, I hope you are doing well. I am trying to add an SRAM controller to my project, but I received the following error in Nios II Eclipse: INFO: Tcl message: "STDIO character device is jtag_uart_0" INFO: Tcl message: "System timer device is sys_timer" SEVERE: CPU "nios2_gen2_0" has no memories connected to its Avalon host(s) WARNING: Tcl script "bsp-set-defaults.tcl " error: CPU "nios2_gen2_0" has no memories connected to its Avalon host(s) SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" SEVERE: [Error] altera_hal_linkerx_generator: Required linker section mappings do not exist: "[.entry, .exceptions, .rodata, .rwdata, .text, .bss, .heap, .stack]" SEVERE: nios2-bsp-create-settings failed. nios2-bsp: nios2-bsp-create-settings.exe failed nios2-bsp hal . ../../led.sopcinfo --cpu-name nios2_gen2_0 failed Please note that I have followed the steps below: IP catalog -> University program -> memory -> SRAM controller. SRAM: sram_avalon_sram_slave is connected to nios_cpu: data_master and instruction_master . nios_cpu -> reset_vector_memory and Exception_vector_memory is to sram.avalon_sram_slave. The base address from SRAM is 0x0000_0000. I have created the top entity module in verilog and all pins are connected. The generated SOPCINFO file for the nios_cpu module has the the above info : <assignment> <name>embeddedsw.configuration.exceptionSlave</name> <value>sram.avalon_sram_slave</value> </assignment> <assignment> <name>embeddedsw.configuration.resetOffset</name> <value>0</value> </assignment> <assignment> <name>embeddedsw.configuration.resetSlave</name> <value>sram.avalon_sram_slave</value> </assignment> Note: Board Altera DE2-115. Quartus version 22.1. No errors if i try other projects without SRAM. I would appreciate any advice on this issue. Thank you.
Pass a generic or make generic/constant available via qsys
Hi guys I wanted to ask if there's a possibility to either pass a generic/constant argument to qsys IP or make the defined generic/constant available. The idea is to define the value of an SPI clock speed only at one place and everything else follows suit. Right now we just instantiate a standard IP block and set the value manually and there's another VHDL file that also utilises the SPI but doesn't know the SPI clock speed resp. we need to manually define it which could be theoretically forgotten if someone changes the value in qsys. I appreciate any replies and wish a nice time. Kinda regards Luigi
