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ingemilo's avatar
ingemilo
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1 month ago

Floating point operation on Cyclone 10 GX

Hello, I have a few questions regarding the way DSP resources are used in the FPGA I’m working with, a Cyclone 10 GX 10CX220YF780I5G. I want to perform an FMA (Fused Multiply-Add) operation using one of the available IPs in the catalog for floating-point operations, but I suspect that the one I’m currently using doesn’t execute the operation jointly as a + b * c; instead, it performs a + (b * c), which leads to errors due to intermediate rounding. The IP I’m using is Floating Point Functions FPGA IP, but there are others available that I believe might accomplish the same operation, such as Floating Point Hardware 2 Multi‑Cycle Intel FPGA or Native Floating Point DSP Cyclone 10 GX FPGA. I can’t find any information in the documentation about whether these operations are fused or not.

Does anyone have any information on this? Thanks in advance.

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5 Replies

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi,

     

    Thank you for filing this case and sharing the details. I appreciate your patience. Please allow me some time to review the information, and I’ll get back to you as soon as possible. 

  • CheepinC_altera's avatar
    CheepinC_altera
    Icon for Regular Contributor rankRegular Contributor
    1 month ago

    Hi,

     

    Thank you for your question. Based on your inquiry regarding the C10GX floating‑point DSP IP and its rounding behavior, I reviewed the available C10GX documentation. I was not able to find any reference indicating support for fused multiply‑add (FMA) operations, which suggests that FMA may not be implemented in this IP.

     

    As a next step, could you try performing the same test using the Native Floating-Point DSP IP to see if there is any different in the observation.

     

    If you have additional questions or need further clarification, please feel free to let me know. Thank you.

    • ingemilo's avatar
      ingemilo
      Icon for New Contributor rankNew Contributor
      1 month ago

      Hi,

      thank you for the replay. I have tried with the Native Floating-Point DSP IP and it seems that the issue I was attributing to rounding errors has been resolved by using that IP, though I should run more thorough tests—even so, the differences are indeed quite significant. 

      In any case, in my opinion, it would be advisable to have clearer documentation regarding each of the IPs available in Quartus.

       

      Thank you.

      • CheepinC_altera's avatar
        CheepinC_altera
        Icon for Regular Contributor rankRegular Contributor
        1 month ago

        Hi Frank,

         

        Thank you for the update. I’m glad to hear that the Native Floating‑Point DSP IP has resolved the rounding issue. From my understanding, the Native DSP IP allows users to access the DSP block directly, without relying on inference.

         

        Please let me know if you have any questions or concerns. Thank you.

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    1 month ago

    Hi,
    I believe specification of Multiply Accumulation operation in IP user guide is quite clear

       Out(t) = [Ay(t) * Az(t)] + Out (t-1) 

    But it's essentially a question of hardware features. Description of DSP block architecture in Device Handbook clarifies that FP adder output is a 32-bit word, no features to recirculate a result with higher resolution as required by FMA.

    Regards
    Frank