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Occasional Contributorrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the top.
background: clk freq is 416Mhz; all design use asynchronous reset;
after fitting all design, the timing report about recovery violation has -1.8ns.
for one timing path, the start point is reset_sync flop2, the end point is aclr port of one flop in the module B. from the following figure 1, I find the distance start point and end point is not far apart but the routing delay is nearly 4.386ns. and How I fix the timing? Doesn't the reset route go through global network?
figure 1:
for compasion，I have taken the follwoing screenshot of the common path routing as figure 2
here, the path from start point pll to clk port of reset_sync flop spans nearly the fabric fpga, but the actual routing delay is only 4.04ns.
figure 2:
13 Replies
KennyT_alteraSuper Contributor
Can you attached your design.qar file for investigation?
When you report the tuming that have -1.8ns recovery violation, are they using a different clock or same clock?
- zjj
oh, sorry! launch clk and capture clk is not same clock. but the two clock is from one pll and is in the same clock group.
- KennyT_altera
It will be better that you send us your design.qar, if you have concern send publicly, let me know.
In the mean time, you may take a look into the reset strategy here: https://docs.altera.com/r/docs/683539/25.1.1/an-917-reset-design-techniques-for-hyperflex-architecture-fpgas/asynchronous-reset-design-strategies
- zjj
oh, sorry! launch clk and capture clk is not same clock.
sstrellGenerate a detailed slack/path report in the timing analyzer (Report Timing) to understand all the resources the paths that are failing are going through and post that report here (Data Arrival Path and Data Required Path).
- zjj
- KennyT_altera
Check the userguide again for the synchronizer, I remember you will need to set false path for different clock.
- KennyT_altera
Since there are no further question, we shall close this thread
