Forum Discussion
zjj
Occasional Contributor
Occasional Contributorrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the t...
zjjOccasional Contributor
Occasional Contributoroh, sorry! launch clk and capture clk is not same clock. but the two clock is from one pll and is in the same clock group.
KennyT_altera
Super Contributor
Super ContributorIt will be better that you send us your design.qar, if you have concern send publicly, let me know.
In the mean time, you may take a look into the reset strategy here: https://docs.altera.com/r/docs/683539/25.1.1/an-917-reset-design-techniques-for-hyperflex-architecture-fpgas/asynchronous-reset-design-strategies
