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RHobb's avatar
RHobb
Icon for Occasional Contributor rankOccasional Contributor
1 month ago
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ModelSim Intel FPGA Ed. 2020.1 not updating changes to HDL File

I have ModelSim open and Quartus Prime Lite v. 22.1, while I'm simulating,  I often make changes back to the Quartus, but when I reload the design into ModelSim, it cold-archives the initial HDL file and references that file instead of the changes I make in Quartus. No matter how many times I recompile the code for both the wrapper function and main entity, it always goes back to the original? How is this possible? Does ModelSim copy the file into it's own directory and simply references it? 

I've spent days trying to figure this out, wihtout creating a new project and adding the changed code to it, how can I force it to use the updated files?

  • This is a very common point of confusion. ModelSim does **not** directly read your source HDL files at simulation time — it compiles them into a compiled library (by default the `work` library directory on disk). When you "reload" or "restart" the simulation inside ModelSim, it re-elaborates from those already-compiled library files, **not** from your updated source. That's why you keep seeing the original behaviour — the compiled library is stale.

    Here's the root cause and the fix:

    Why it happens



    The simulation workflow requires assembling a script that compiles the simulation files into libraries, elaborates the top-level testbench, and then runs the simulation model. ModelSim works from the compiled library output of that compilation step, not directly from your HDL sources. FPGA Simulation Generic Workflow Simply reloading or restarting within ModelSim skips the compilation step entirely.

    What you need to do after every Quartus recompile



    1. Recompile in Quartus first. Click Processing > Start Compilation to compile the design and regenerate the simulation files (including the .do script). The Messages window indicates when compilation is complete. ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition
    2. Re-run the RTL Simulation launch from Quartus. Click Tools > Run Simulation Tool > RTL Simulation. The Quartus Prime software launches ModelSim – FPGA Edition ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition with a freshly generated script that recompiles all the HDL into the work library from scratch. This is the clean way to pick up your changes.
    3. Alternatively, if you prefer to stay inside ModelSim, re-execute the generated .do script from the Transcript window (e.g. do simulation/mentor/msim_setup.tcl or whichever script Quartus generated). Platform Designer generates a ModelSim simulation script (msim_setup.tcl) that compiles the required files for simulation and sets up commands to load the simulation. You can run this script in ModelSim to compile, elaborate, or load for simulation. Embedded Design Handbook Re-running it forces recompilation of the updated sources.


    Bottom line: "Restart" or "Run -all" inside an open ModelSim session only re-runs an already-elaborated model. You must re-execute the compilation script (or use Tools > Run Simulation Tool > RTL Simulation from Quartus) to push your HDL edits into the work library and make ModelSim see them. Once you build that habit into your edit → compile in Quartus → re-run script → simulate loop, the stale-file problem goes away.

    Note: To continue using AI Responder, please start your next inquiry with ai_responder

    Disclaimer (Beta): The AI Responder is currently provided as a beta feature. AI-generated responses may contain errors or omissions. Please verify technical guidance with official Altera documentation before implementation.

    Thank you very much.

8 Replies

  • ai_responder's avatar
    ai_responder
    Icon for Community Manager rankCommunity Manager

    This is a very common point of confusion. ModelSim does **not** directly read your source HDL files at simulation time — it compiles them into a compiled library (by default the `work` library directory on disk). When you "reload" or "restart" the simulation inside ModelSim, it re-elaborates from those already-compiled library files, **not** from your updated source. That's why you keep seeing the original behaviour — the compiled library is stale.

    Here's the root cause and the fix:

    Why it happens



    The simulation workflow requires assembling a script that compiles the simulation files into libraries, elaborates the top-level testbench, and then runs the simulation model. ModelSim works from the compiled library output of that compilation step, not directly from your HDL sources. FPGA Simulation Generic Workflow Simply reloading or restarting within ModelSim skips the compilation step entirely.

    What you need to do after every Quartus recompile



    1. Recompile in Quartus first. Click Processing > Start Compilation to compile the design and regenerate the simulation files (including the .do script). The Messages window indicates when compilation is complete. ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition
    2. Re-run the RTL Simulation launch from Quartus. Click Tools > Run Simulation Tool > RTL Simulation. The Quartus Prime software launches ModelSim – FPGA Edition ModelSim – FPGA Edition Simulation Quick-Start Quartus Prime Standard Edition with a freshly generated script that recompiles all the HDL into the work library from scratch. This is the clean way to pick up your changes.
    3. Alternatively, if you prefer to stay inside ModelSim, re-execute the generated .do script from the Transcript window (e.g. do simulation/mentor/msim_setup.tcl or whichever script Quartus generated). Platform Designer generates a ModelSim simulation script (msim_setup.tcl) that compiles the required files for simulation and sets up commands to load the simulation. You can run this script in ModelSim to compile, elaborate, or load for simulation. Embedded Design Handbook Re-running it forces recompilation of the updated sources.


    Bottom line: "Restart" or "Run -all" inside an open ModelSim session only re-runs an already-elaborated model. You must re-execute the compilation script (or use Tools > Run Simulation Tool > RTL Simulation from Quartus) to push your HDL edits into the work library and make ModelSim see them. Once you build that habit into your edit → compile in Quartus → re-run script → simulate loop, the stale-file problem goes away.

    Note: To continue using AI Responder, please start your next inquiry with ai_responder

    Disclaimer (Beta): The AI Responder is currently provided as a beta feature. AI-generated responses may contain errors or omissions. Please verify technical guidance with official Altera documentation before implementation.

    Thank you very much.

  • Hi RHobb,

    On top of above, could you please provide the design .qar file packaged in a .zip file? The forum currently only supports .zip uploads.
     

    If possible, it would also be very helpful if you could share:

    • Any relevant screenshots of the issue.
    • The step-by-step workflow you followed, from project setup through simulation, including the command used to recompile and reload the design in ModelSim.
    • The operating system you are using.

    With this information, we'll be able to better understand the behavior and try to reproduce it on our side.
     

    Thank you! 
     

    Regards, 
    ZiYingE_Altera

    • RHobb's avatar
      RHobb
      Icon for Occasional Contributor rankOccasional Contributor

      I'm sorry I'm unable to upload my code, as this is protected IP.

      Please note however, that having Quartus Prime Light open at the same time ModelSim is open, when changing, modifying or adding files to a project in Quartus, can have read/write errors on ModelSim if that same file is being opened and simulations run. I have found that by refreshing the screen in ModelSim, can help, it asks to reload the project and compile. But I'm still having mixed results where it's cold archiving a copy of the original file, while I make changes in Quartus, and both ModelSim is open. 

      As a quick solution, that is tedious, I simply just remove the source files from ModelSim, then add them back after I made changes in Quartus, and seems to work this way. Not sure why ModelSim would be referencing an original copy after I already made changes in Quartus?

      • ZiYingE_Altera's avatar
        ZiYingE_Altera
        Icon for Contributor rankContributor

        Hi RHobb,
         

        Thank you for marking the AI Responder reply as the solution. We would appreciate your feedback for our continuous improvement.


        Could you please share which suggestion worked best for you?


        In your previous reply, you mentioned that removing the source files from ModelSim and adding them back after making changes in Quartus helped. 

        Could you let us know if this was the approach that resolved the issue, or if another recommendation from the AI Responder was helpful?


        Thank you in advance for your feedback.
         

        Regards, 
        ZiYingE_Altera

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,

    ModelSim and QuestaSim normally don't copy or "archive" source files, unless you specify so when adding the files to simulation project. As stated above, you however need to recompile modified files in ModelSim before restarting the simulation. Compile in ModelSim is much faster than in Quartus which isn't required for simulation.

    Regards Frank

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor

    Hi,
    additional remark about requiring prior compilation in Quartus. NativeLink simulation flow needs apparently a compiled hierarchy to build the compilation script. If the design structure changes, a recompilation is necessary for NativeLink flow, functional changes of entities need only recompilation in simulator. This can be achieved in NativeLink flow by copying respective compile commands from .do script and pasting in Simulator gui.

    Regards
    Frank

    • ZiYingE_Altera's avatar
      ZiYingE_Altera
      Icon for Contributor rankContributor

      Hi RHobb,

      Thanks to FvM, Frank for the detailed explanation.

      Hereby attached with the additional steps.
      For the changes made within single HDL file:

      1. Save the modified HDL file in Quartus.
      2. Stop only the active simulation, leaving the ModelSim window open: quit -sim
      3. Recompile the modified HDL file directly. Use vlog for Verilog/SystemVerilog or vcom for VHDL: vlog -work work C:/path/to/changed_file.sv
      4. Reload the testbench: vsim work.<testbench_name>
      5. Run the simulation: run -all

      If the design hierarchy, file list, or project structure has changed, a full recompile is recommended:

      1. Stops the current simulation but leaves the ModelSim application open: quit -sim
      2.  Clears the compiled work library: vdel -lib work -all
      3. Creates the new work library: vlib work 
      4. Maps ModelSim's work name to that library: vmap work work
      5. Rerun complete .do script

      After running these steps, feel free to let us know the outcome and whether the issue persists.

      Thank you!

      Regards, 
      ZiYingE_Altera