MAX10 ADC - getting it to simulate in Modelsim
Hi, I'm setting up a new project - actually a rework of a 7 year old project were we had massive tools problems with the ADC, some of which I think were specific to Quartus 17. I have regenerated the ADC IP in Quartus 18.1. I have manually created the simulation in Modelsim 10.5b. I have added all the ADC files I can find to the Modelsim project, as shown in the attached screenshot. When I run the simulation, all the ADC outputs are floating. Any clues as to what I am going wrong, please? I tried running the msim_setup.tcl from the Modelsim command line, but this made no difference. Searching this forum, I wonder if it has something to do with fiftyfivenm_adcblock_primitive_wrapper.v, but the solution eludes me, since I have compiled this. Attached: screenshot of my modelsim project, the generated IP code, and my vhdl which instantiates the ADC. Thanks, Rob
QPP 26.1.0 Tools->Generate Simulator Setup Script produces no output
Hello, I have a relatively simple Agilex 3 QPP 26.1.0 project with four IPs on Win 11. Today after adding the latest IP block, running Tools->Generate Simulator Setup Script produces no output when executing the command. I can see from the Quartus log that "--spd" is not passed, and I believe this is the problem. If I run ip-sim-script in the Quartus command line and include the "--spd" option, the correct sim folders and files are produced. I do not see this same problem when working with the same project on Ubuntu Linux. What would cause "--spd" not to be passed? Note that the *.spd files do exist. Thank you.Compile option not saved (reversed to default)
Quartus std 25.1 / Questa Altrera FPGA Ed. 64 2025.2 My project use systemverilog all designs. launch RTL Simulation/Questa from Quartus , Everytime error happen not treated as designs are systemverilog. Opening "Compile->Compile option->verilog" and chage "default" to "systemverilog" then re-load design by "do ***_run_msim_rtl_systemverilog.do" command, no error happens. But next Questa launch, same error happend and "Compile option" reversed to "default" not saved.
FIR IP configured for Interpolation
Why does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
