How to generate a netlist when the design includes encrypted sources
I would like to ship my design to a customer as an encrypted netlist, however I am unable to create the netlist after a successful run, because my design includes encrypted RTL (unable to change this). I am running the following command (after running synthesis and P&R): quartus_eda my_project --simulation --format=vhdl --tool=modelsim -c my_project_revision I get the following error: Error (18580): Cannot generate netlist output files because the design includes encrypted source files: "/path/to/encrypted/rtl/file.vhdp" I see here that this was planned to be possible in "future" Quartus Prime updates, but I am using 26.1 and no such update has been made. I have also attempted to run the following command, with the exact same result: quartus_eda my_project --resynthesis --tool=modelsim Any help would be appreciated; perhaps this is plainly impossible, or perhaps there is some work-around. Thank you!
Questa FPGA Starter Edition: Fatal WLF Error when restarting sim
Simulating some SystemVerilog code (example attached) on Questasim Starter Edition 24.1 or 25.1, when clicking on "restart" on the gui (or typing restart in the console), QuestaSim crashes and gives the following error: ** Error: Fatal WLF Error (2): allocateArchiveNumbers: unknown opcode error: 0 1 I have attached a minimal reproducible example, along with the transcript. On the example, I have found the crash only occurs when passing req_i.b to the "control_decoder" module. Passing req_i.a works fine. Defining type_t with just one member logic b also works. On the Makefile, removing -pedanticerrors also prevents the crash. ThanksFIR IP configured for Interpolation
Why does my Altera FIR IP, configured for interpolation by 80, produce the expected outputs when I provide 3 input samples, but fail to produce the expected behavior when I provide 10 input samples? In this case, the FIR IP keeps tready asserted high, but only generates 4 valid outputs. What could be causing this behavior? I am simulating this in Quartus Prime Lite Edition.
RTL Simulation fails with: couldn't execute ip-setup-simulation: invalid argument
Hi , Error: Failed to run ip-setup-simulation: couldn't execute "c:\altera_pro\26.1\quartus\..\vds\bin\ip-setup-simulation": invalid argument I have been facing this issue since morning, unable to run the simulation, yesterday it was working fine. Even tried regenerating IP files also today, but got the same error. Any help is appreciated. Regards, Sai@2403RTL Simulation fails with: couldn't execute ip-setup-simulation: invalid argument
Hello, I am using Quartus Prime Pro Edition 25.3.1 on Windows 10/11. RTL simulation fails immediately with the following error: Error: Failed to run ip-setup-simulation: couldn't execute "ip-setup-simulation": invalid argument Error: Simulation flow failed Error(23031): Evaluation of Tcl script c:/altera_pro/25.3.1/quartus/common/tcl/internal/nativelink/qnativesim.tcl unsuccessful Additional stack trace: Simulation TCL script failed with errorCode: 1 (procedure "iputf_call_script_gen" line 1) invoked from within "iputf_call_script_gen $spd_file_list" I already checked the following: - Same error occurs for all projects - Same error occurs in Quartus Pro 25.1 and 25.3.1 - Same error occurs after deleting db/, incremental_db/, simulation/ folders - PATH conflict removed (only one vsim exists in PATH) - `vsim -version` shows: "Questa Altera FPGA Edition-64 vsim 2025.2 Simulator" - `where vsim` returns only: C:\altera_pro\25.3.1\questa_fe\win64\vsim.exe - `Generate Simulator Setup Script for IP` also fails - IP regenerate fails with: "Failed to retrieve Quartus project IP search paths" I also noticed that Quartus reports: "Questa Altera FPGA Edition simulator is not supported for simulation library compilation." Questions: 1. Is Questa Altera FPGA Edition (questa_fe) unsupported for Quartus Pro 25.x NativeLink RTL simulation? 2. Is this a known issue with ip-setup-simulation or qnativesim.tcl? 3. Does Quartus Pro require Questa Intel FPGA Edition/full Questa instead of questa_fe? 4. Is there a workaround besides manually running Questa simulation scripts? Thank you.
Licencing error for Questa - Altera FPGA Starter Edition 2025.2 (Quartus Prime Pro 25.1std)
Hello, I have the following error window show up after trying to launch Questa. I have downloaded the license, and created a system variable as shown in the other picture. I also tryed following solutions in similar isues discused here, but to no help. I have downloaded this wersion: Intel® Quartus® Prime Lite Edition Design Software Version 25.1 for Windows using the full installer Intel® Quartus® Prime Lite Edition Installer (SFX)
Questa-sim waveform- How to export to CSV?
I am using Questasim for doing waveform debug. I want to dump current waveform as CSV to apply some analytics on it. When I go to FIle > Export option "waveform" option is greyed out and is not available. I see "Image" option which I dont want; and "VCD" option is also greyed out. please help me on how can i export waveforms I see into CSV format.
