Hard Reset Required After Each Boundary Scan Operation
Hello there, I am working on a project involving JTAG operations (specifically boundary scan on the data register) using Quartus Prime Standard (v24) and a USB-Blaster cable. Issue: After every scan operation, I need to perform a hard reset on the device connected to the cable. If I skip the hard reset, the next scan returns incorrect TDO values. I have tried performing a soft reset after each operation, but this does not resolve the issue. Only a hard reset consistently allows me to get the correct TDO results. Sequence being used (via my Python library executing TCL commands): open_device -hardware_name {USB-Blaster [USB-0]} -device_name {@1: JTAG_DEVICE (0x12345678)} device_lock -timeout 10000 device_ir_shift -ir_value 0x00000000 puts "TDO is: 0x[device_dr_shift -length 48 -value_in_hex]" device_unlock close_device Notes: - The Python library manages TCL sessions in a dedicated terminal. - I observe the same issue when performing these operations using Quartus directly. My question: Is there a Quartus or TCL command or procedure that can help avoid the need for a hard reset after each boundary scan operation? Or is there a way to reliably ensure the correct TDO value is returned every time without hard resetting the device? Thank you for your assistance.Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, Alkesh
Licencing error for Questa - Altera FPGA Starter Edition 2025.2 (Quartus Prime Pro 25.1std)
Hello, I have the following error window show up after trying to launch Questa. I have downloaded the license, and created a system variable as shown in the other picture. I also tryed following solutions in similar isues discused here, but to no help. I have downloaded this wersion: Intel® Quartus® Prime Lite Edition Design Software Version 25.1 for Windows using the full installer Intel® Quartus® Prime Lite Edition Installer (SFX)
EDA_MAINTAIN_DESIGN_HIERARCHY obsolete?
Hi Community, I'm using Quartus Pro 25.1.1 and for simulation need to enable EDA_MAINTAIN_DESIGN_HIERARCHY during eda netlist writing. I wasn't able to find it somewhere in the settings and setting it via global assignment in qsf leads to this: # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation" # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation" Does anyone know how to turn the hierarchy preservation on? Thanks in advance!Questa FSE Installation: Env Variable Incorrect
Documentation for installation of Questa FSE: https://www.intel.com/content/www/us/en/docs/programmable/683472/25-3/and-software-license.html Indicates to export the `SALT_LICENSE_FILE`to the location of the necessary license file. This variable should actually be `SALT_LICENSE_SERVER`. Wanted to post my finding here in case any others have run into this. vsim -version Questa Altera Starter FPGA Edition-64 vsim 2025.2 Simulator 2025.05 May 31 2025 uname -a Linux dev 6.14.0-36-generic #36~24.04.1-Ubuntu SMP PREEMPT_DYNAMIC Wed Oct 15 15:45:17 UTC 2 x86_64 x86_64 x86_64 GNU/Linux
The FIFO has no output waveform
Hi, I am currently using Quartus Prime Lite 24.1 and the 10M02M153C8G device to implement an 8Kx9 SYNC FIFO. I generated the design directly using the IP CORE. Initially, my tests successfully produced output waveforms. However, I must have changed a setting unintentionally, as I am now unable to simulate the output. Even previous projects that worked before are no longer producing any waveforms. I subsequently observed the following messages in the Simulation flow progress: Warning: sclr - signal not found in VCD. Warning: wrreq - signal not found in VCD. These warnings are appearing for multiple signals, as shown in the image or attachment (referring to the image/attachment). I have already tried reinstalling the software and updating the license options, but the issue persists. Could you please advise on the cause of this problem and how to resolve it? Thank you for your assistance.
