Introducing the Altera Community AI Responder — Beta
Altera is introducing the AI Responder, an assistant built into the Altera Community to help provide faster, context-aware guidance for Altera product questions. It uses relevant public Altera documentation and Knowledge Database content, with coverage continuing to expand. The AI Responder may provide source references and can hand off complex or out-of-scope questions to an Altera subject-matter expert. As a beta feature, responses may contain errors or omissions, so please review the sources and verify technical guidance against official Altera documentation before implementation. If the response does not fully address your question, add more context and tag ai_responder to continue the discussion. We welcome your feedback as we improve the Community experience.
Questa warning vsim-3473 Component instance is not bound.
I am using Quartus Prime Pro 25.3 and Questa Altera Starter FPGA Edition-64 2025.2. I am trying to simulate a design with numerous Altera IP. I get the "not bound" warning for the many, possibly all, of the Altera IP. I have searched online and this forum. I see the same problem identified with ModelSim. I could not find anything specifically Questa. I have tried various posted solutions but have had no success. I generated simulation models for all IP in Quartus. For one of the IP, I tried creating the simulation model in VHDL and Verilog and tried Traditional and Qrun QuestSim flow selection. I checked the QuestaSim box for which simulator script will be generated. I found some solutions talking about using the command line in Questa. I very much prefer to remain in in the GUI for all commands.
MAX10 ADC - getting it to simulate in Modelsim
Hi, I'm setting up a new project - actually a rework of a 7 year old project were we had massive tools problems with the ADC, some of which I think were specific to Quartus 17. I have regenerated the ADC IP in Quartus 18.1. I have manually created the simulation in Modelsim 10.5b. I have added all the ADC files I can find to the Modelsim project, as shown in the attached screenshot. When I run the simulation, all the ADC outputs are floating. Any clues as to what I am going wrong, please? I tried running the msim_setup.tcl from the Modelsim command line, but this made no difference. Searching this forum, I wonder if it has something to do with fiftyfivenm_adcblock_primitive_wrapper.v, but the solution eludes me, since I have compiled this. Attached: screenshot of my modelsim project, the generated IP code, and my vhdl which instantiates the ADC. Thanks, Rob
QPP 26.1.0 Tools->Generate Simulator Setup Script produces no output
Hello, I have a relatively simple Agilex 3 QPP 26.1.0 project with four IPs on Win 11. Today after adding the latest IP block, running Tools->Generate Simulator Setup Script produces no output when executing the command. I can see from the Quartus log that "--spd" is not passed, and I believe this is the problem. If I run ip-sim-script in the Quartus command line and include the "--spd" option, the correct sim folders and files are produced. I do not see this same problem when working with the same project on Ubuntu Linux. What would cause "--spd" not to be passed? Note that the *.spd files do exist. Thank you.
Xcelium Simulation using XRUN with Verilog Configurations defining Library Search Order
I have an AgileX based design using Quartus 26.1.0.110 and Simulating with Xcelium 24.09.005. If I simulate the FPGA entirely standalone using this combination and embracing the xcelium/xcelium_setup.sh approach I can have some success. So I know that everything within the FPGA is resolving. If I attempt to develop a Verilog Configuration for the design by integrating the xmelab run for the resolved libraries found in order to develop my "default liblist" within the Verilog configuration and then migrate the flow to Cadence XRUN it fails. My XRUN environment does NOT have a cds.lib or hdl.var files as they are empty. Everything in this flow is to be governed by the XRUN environment. I need the XRUN flow to run to further integrate this FPGA into a larger multiple Mixed Signal ASICs. Can someone tell me the correct order that should be present in the "default liblist" for a Verilog Configuration? The errors I get are unresolved cells in library where everything inside the rest of the error is inside the encrypted Altera libraries. So it is impossible to debug exactly which cell it is referencing. Something like: xmelab: *E, BILCNF: Cell '{Name Protected*}' not found for instance '{*Name Protected*}' through configuration '{*Name Protected*}' The cell listed was: ip7521serdes_uxs2t1r1gpd_pipe_msvmodelknobmod Has anyone tried this? Could Altera Engineering provided a defined expected library order for the lowest level encrypted libraries? Thanks, Thomas D. TessierQuesta Starter Edition: Nothing can be added to Wave window
Hello, I cannot add any objects to the Wave window, by right-clicking nodes in the Sim window and selecting the Add Wave command. Even the objects in my Sim.v that I am using to stimulate the DUT cannot be added to the Wave Window. This method worked in the ModelSim. What am I doing wrong? Please see attached screen shots. Regards, Mark
