Error Modelsim-Altera for integer type ports in adder
I searched the forums and found that others were experiencing the same problem, but it seems they hadn't found a solution. I tried writing a similar program a long time ago; it worked fine in Quartus 13, but everything started having problems in Quartus 24. I don't know how to fix it. Please help me. https://community.altera.com/discussions/quartus-prime/error-modelsim-altera-for-integer-type-ports/333570?utm_source=chatgpt.com LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY ex1 IS PORT ( A, B : IN integer range 0 to 15; Y : OUT integer range 0 to 31); END ex1; ARCHITECTURE Behavior OF ex1 IS SIGNAL Z: integer range 0 to 31; BEGIN Z <= A+B; Y <= Z WHEN (z<10) ELSE Z+6; END Behavior; this is my code , this is my error information: Determining the location of the ModelSim executable... Using: C:/intelFPGA/20.1/modelsim_ase/win32aloem To specify a ModelSim executable directory, select: Tools -> Options -> EDA Tool Options Note: if both Questa Intel FPGA Edition and ModelSim executables are available, Questa Intel FPGA Edition will be used. **** Generating the ModelSim Testbench **** quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source="C:/sample/adder/Waveform.vwf" --testbench_file="C:/sample/adder/simulation/qsim/Waveform.vwf.vht" Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition Info: Copyright (C) 2025 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Apr 6 01:08:46 2026 Info: Command: quartus_eda --gen_testbench --tool=modelsim_oem --format=vhdl --write_settings_files=off adder -c adder --vector_source=C:/sample/adder/Waveform.vwf --testbench_file=C:/sample/adder/simulation/qsim/Waveform.vwf.vht Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Completed successfully. **** Generating the functional simulation netlist **** quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory="C:/sample/adder/simulation/qsim/" adder -c adder Info: ******************************************************************* Info: Running Quartus Prime EDA Netlist Writer Info: Version 24.1std.0 Build 1077 03/04/2025 SC Lite Edition Info: Copyright (C) 2025 Altera Corporation. All rights reserved. Info: Your use of Altera Corporation's design tools, logic functions Info: and other software and tools, and any partner logic Info: functions, and any output files from any of the foregoing Info: (including device programming or simulation files), and any Info: associated documentation or information are expressly subject Info: to the terms and conditions of the Altera Program License Info: Subscription Agreement, the Altera Quartus Prime License Agreement, Info: the Altera IP License Agreement, or other applicable license Info: agreement, including, without limitation, that your use is for Info: the sole purpose of programming logic devices manufactured by Info: Altera and sold by Altera or its authorized distributors. Please Info: refer to the Altera Software License Subscription Agreements Info: on the Quartus Prime software download page. Info: Processing started: Mon Apr 6 01:08:47 2026 Info: Command: quartus_eda --write_settings_files=off --simulation=on --functional=on --flatten_buses=off --tool=modelsim_oem --format=vhdl --output_directory=C:/sample/adder/simulation/qsim/ adder -c adder Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Info (204019): Generated file adder.vho in folder "C:/sample/adder/simulation/qsim//" for EDA simulation tool Info: Quartus Prime EDA Netlist Writer was successful. 0 errors, 1 warning Info: Peak virtual memory: 4737 megabytes Info: Processing ended: Mon Apr 6 01:08:48 2026 Info: Elapsed time: 00:00:01 Info: Total CPU time (on all processors): 00:00:00 Completed successfully. **** Generating the ModelSim .do script **** C:/sample/adder/simulation/qsim/adder.do generated. Completed successfully. **** Running the ModelSim simulation **** C:/intelFPGA/20.1/modelsim_ase/win32aloem/vsim -c -do adder.do Reading pref.tcl # 2020.1 # do adder.do # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 01:08:48 on Apr 06,2026 # vcom -work work adder.vho # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Loading package altera_lnsim_components # -- Loading package VITAL_Timing # -- Loading package VITAL_Primitives # -- Loading package cyclonev_atom_pack # -- Loading package cyclonev_components # -- Loading package std_logic_arith # -- Compiling entity adder # -- Compiling architecture structure of adder # End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # Model Technology ModelSim - Intel FPGA Edition vcom 2020.1 Compiler 2020.02 Feb 28 2020 # Start time: 01:08:48 on Apr 06,2026 # vcom -work work Waveform.vwf.vht # -- Loading package STANDARD # -- Loading package TEXTIO # -- Loading package std_logic_1164 # -- Compiling entity adder_vhd_vec_tst # -- Compiling architecture adder_arch of adder_vhd_vec_tst # End time: 01:08:48 on Apr 06,2026, Elapsed time: 0:00:00 # Errors: 0, Warnings: 0 # vsim -c -t 1ps -L cyclonev -L altera -L altera_mf -L 220model -L sgate -L altera_lnsim work.adder_vhd_vec_tst # Start time: 01:08:48 on Apr 06,2026 # Loading std.standard # Loading std.textio(body) # Loading ieee.std_logic_1164(body) # Loading work.adder_vhd_vec_tst(adder_arch) # Loading altera_lnsim.altera_lnsim_components # Loading ieee.vital_timing(body) # Loading ieee.vital_primitives(body) # Loading cyclonev.cyclonev_atom_pack(body) # Loading cyclonev.cyclonev_components # Loading ieee.std_logic_arith(body) # Loading work.adder(structure) # ** Fatal: (vsim-3807) Types do not match between component and entity for port "A". # Time: 0 ps Iteration: 0 Instance: /adder_vhd_vec_tst/i1 File: adder.vho Line: 40 # FATAL ERROR while loading design # Error loading design Error loading design # End time: 01:08:49 on Apr 06,2026, Elapsed time: 0:00:01 # Errors: 1, Warnings: 0 Error.
Questa – Altera FPGA Edition simulator licensing
Hello all, I am trying to get this simulator to work with a fixed license file but when trying to open it I get the licensing error shown below Currently my environment is configured so that environment variable LM_LICENSE_FILE points to the .dat fixed license file. SALT_LICENSE_SERVER environment variable doesn't exist in my environment. Am i missing anything regarding the configuration of my environment? Could somebody please help me solve this licensing problem? Thank you very much in advance for your help. Best Regards, Eduardo.
Quartus Eda_Writer keeps crashing
Quartus Prime v25 keeps crashing at the eda_writer step during the flow on Windows 11. I have tried different Quartus versions (II v13.1, Prime Lite v25, Prime Standard v25). All of them crashed at this step multiple times. Is this an issue with the design that I am trying to implement? I searched for this error on Google and I found a message that said it was a bug that was fixed in version 21.1. Strange that its still occuring now in v25 standard. Problem Details Error: Internal Error: Sub-system: WSC, File: /quartus/neto/wsc/wsc_hierarchy_builder.cpp, Line: 1097 m_bp_manager != NULL Stack Trace: 0x48eca: WSC_HIERARCHY_BUILDER::build_map_from_partitions + 0x8a (NETO_WSC) 0x46dd5: WSC_HIERARCHY_BUILDER::build_hierarchy_from_partitions + 0x35 (NETO_WSC) 0x45e1b: WSC_HIERARCHY_BUILDER::build + 0x22b (NETO_WSC) 0x16282: QNETO_START::build_hierarchy_netlist + 0x242 (quartus_eda) 0x28548: QNETO_START::generate_simulation_files + 0x688 (quartus_eda) 0x1a1e3: QNETO_START::generate_eda_files + 0x43 (quartus_eda) 0x33fd0: qneto_execute + 0x210 (quartus_eda) 0xa79b: QNETO_FRAMEWORK::execute + 0x26b (quartus_eda) 0x10b5f: qexe_do_normal + 0x22f (comp_qexe) 0x16fa0: qexe_run + 0x420 (comp_qexe) 0x18012: qexe_standard_main + 0xb2 (comp_qexe) 0x10d17: qneto_main + 0x77 (quartus_eda) 0x12208: msg_main_thread + 0x18 (CCL_MSG) 0x13b18: msg_thread_wrapper + 0x78 (CCL_MSG) 0x15f13: mem_thread_wrapper + 0x73 (ccl_mem) 0x11a41: msg_exe_main + 0xa1 (CCL_MSG) 0x36423: __scrt_common_main_seh + 0x10b (quartus_eda) 0x2e8d6: BaseThreadInitThunk + 0x16 (KERNEL32) 0x8c53b: RtlUserThreadStart + 0x2b (ntdll) End-trace Executable: quartus Comment: None System Information Platform: windows64 OS name: Windows 10 OS version: 10.0 Quartus Prime Information Address bits: 64 Version: 25.1std.0 Build: 1129 Edition: Standard Edition
Integrating Cocotb to Quartus using Native link
To integrate cocotb to Quartus Prime Native link and Questa, among a few environment variables needed, one has to set the following `vsim` option: `-foreign "cocotb_init $(cocotb-config --lib-name-path fli questa)"` see here: https://docs.cocotb.org/en/stable/custom_flows.html This needs to be actually slightly adapted to questa, and the following option should be used instead: `-foreign \"cocotb_init [exec cocotb-config --lib-name-path fli questa]\"` With all this information in hand, I try to add `questa=-foreign \"cocotb_init [exec cocotb-config --lib-name-path fli questa]\"` in Assignments >> Settings >> EDA Tools Settings >> Simulation Flow Settings >> Simulation Options, and I get the following error in Quartus: Info(125063): set_global_assignment -name EDA_EXTRA_SIM_OPTION "questa=-foreign \\\"cocotb_init [exec cocotb-config --lib-name-path fli questa]\\\"" -section_id eda_simulation Error(125048): Error reading Quartus Prime Settings file /home/msilvaol/LATOME_HLS/firmware/src/latome_fw/s2p_bram/s2p_bram.qsf, line 49 And then when I try to start the simulation, I get the following error: Error(23031): Evaluation of Tcl script /home/sw/intel/25.3/quartus/common/tcl/internal/nativelink/qnativesim.tcl unsuccessful The workaround I have at the moment is to do the following: I set Assignments >> Settings >> EDA Tools Settings >> Simulation Flow Settings >> Simulation Options to `questa=COCOTB_CFG` Then, I start the simulation that fails because COCOTB_CFG is not a valid vsim option. I open the file `./simulation/questa/rtlsim/s2p_bram_run_msim_rtl_vhdl.do`, and I replace the line 42 from: ` eval "vsim -t 1ps $pd_libs -L work -L rtl_work -voptargs=\"+acc\" COCOTB_CFG $ELAB_OPTIONS $DPI_LIBRARIES_ELAB s2p_bram_showahead" ` to the actual option that I tried to set in Quartus Prime, as follows: eval "vsim -t 1ps $pd_libs -L work -L rtl_work -voptargs=\"+acc\" -foreign \"cocotb_init [exec cocotb-config --lib-name-path fli questa]\" $ELAB_OPTIONS $DPI_LIBRARIES_ELAB s2p_bram_showahead" Then, I run the .do script again in questa and the simulation with cocotb works using Quartus Prime as the build flow. However, every time the simulation is started again from Quartus Prime, the generated scripts are overwritten, and I have to edit the automatically generated file again. It seems Quartus is parsing the simulation option and adding escape characters in a way that the automatically generated TCL code no longer works. Can you please point out a way that I can set the simulation option correctly?
ModelSim executable not found in C:/intelFPGA_lite/simulation/modelsim Error.
I am having this error message when attempting to run the model sim execution in the University Program VWF. My OS is windows 10, i5 processor. I am running the 23.1 software version. I am using the MAX10 10M50DAF484C7G device (DE10-Lite). from the reading that have done I need to go to tools, Options, EDA Tool Options, under the model sim tab I need to point it to the correct directory. When I search I have assigned the following directory: C:/intelFPGA_lite/simulation/modelsim I get to the modelsim folder and there are no further folders to go into, I have removed and reinstalled the software and I am having the same issue. What am I missing and how can I fix it?
Hard reset with USB-Blaster and Quartus
Hello there, I am working on few JTAG operations using Quartus prime standard (v24) with USB-Blaster (cable). After every operation I need to hard reset to perform the next operation. Unless Hard-reset is performed, the data received in TDO is not correct. Is there any command to make sure we do not have to perform hard-reset (Just to note, soft-reset is always performed). A quick response to this would be appreciated. Thanks in advance :) BR, AlkeshHard Reset Required After Each Boundary Scan Operation
Hello there, I am working on a project involving JTAG operations (specifically boundary scan on the data register) using Quartus Prime Standard (v24) and a USB-Blaster cable. Issue: After every scan operation, I need to perform a hard reset on the device connected to the cable. If I skip the hard reset, the next scan returns incorrect TDO values. I have tried performing a soft reset after each operation, but this does not resolve the issue. Only a hard reset consistently allows me to get the correct TDO results. Sequence being used (via my Python library executing TCL commands): open_device -hardware_name {USB-Blaster [USB-0]} -device_name {@1: JTAG_DEVICE (0x12345678)} device_lock -timeout 10000 device_ir_shift -ir_value 0x00000000 puts "TDO is: 0x[device_dr_shift -length 48 -value_in_hex]" device_unlock close_device Notes: - The Python library manages TCL sessions in a dedicated terminal. - I observe the same issue when performing these operations using Quartus directly. My question: Is there a Quartus or TCL command or procedure that can help avoid the need for a hard reset after each boundary scan operation? Or is there a way to reliably ensure the correct TDO value is returned every time without hard resetting the device? Thank you for your assistance.
Licencing error for Questa - Altera FPGA Starter Edition 2025.2 (Quartus Prime Pro 25.1std)
Hello, I have the following error window show up after trying to launch Questa. I have downloaded the license, and created a system variable as shown in the other picture. I also tryed following solutions in similar isues discused here, but to no help. I have downloaded this wersion: Intel® Quartus® Prime Lite Edition Design Software Version 25.1 for Windows using the full installer Intel® Quartus® Prime Lite Edition Installer (SFX)EDA_MAINTAIN_DESIGN_HIERARCHY obsolete?
Hi Community, I'm using Quartus Pro 25.1.1 and for simulation need to enable EDA_MAINTAIN_DESIGN_HIERARCHY during eda netlist writing. I wasn't able to find it somewhere in the settings and setting it via global assignment in qsf leads to this: # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_MAINTAIN_DESIGN_HIERARCHY ON -section_id eda_simulation" # Obsolete assignment in <Version 25.1> "set_global_assignment -name EDA_GENERATE_FUNCTIONAL_NETLIST OFF -section_id eda_simulation" Does anyone know how to turn the hierarchy preservation on? Thanks in advance!
