cjak
Occasional Contributor
Occasional ContributorQuestaSim - Fatal error simulating altpll-ip
Hi,
I am trying to simulate design including the altpll-ip, but I get this fatal error:
I have changed timescale to ps with no luck.
Any suggestions?
Forum Discussion
7 Replies
cjakReset is at high-level when simulation starts...
Input-frequency is 24MHz...
- RichardT_altera
Super Contributor
Hi cjak
Could you please share the design (Project > Archive Project) and the testbench so I can reproduce the issue on my side?
If you have any confidential IP, you could create and share a simplified design that can replicate the problem, or you may private message me the design.
You will need to zip the .qar design and attach the .zip file in forum.
Regards,
Richard Tan - RichardT_altera
Any update on this?
Regards,
Richard Tan - cjak
Hi, sorry for slow response. I have been away for 2 days.
I rebuilt my project in QuestaSim, and the error is gone, but I do not seem to get the PLL to lock. Do I need to include more than the vhd-file for the PLL in my project?
I am sorry but I cannot send you my project....unfortunately.
- cjak
hm, adding reset to init the PLL caused the error to come back :-)
I added stimuli controlling the areset-input on the PLL. Setting reset high for 10 us, then low.
- RichardT_altera
Have you tried running the simulation using the NativeLink simulation flow?
Without the design files, it is challenging to debug and understand the root cause. If possible, creating a simplified design would help us investigate further.
Otherwise, the currently identified possible root cause is described in the KDB below, which I believe you have already reviewed:
https://community.altera.com/kb/knowledge-base/fatal-sigfpe-floating-point-exception/342914
Regards,
Richard Tan
- cjak
No, I have not tried NativeLink simulation flow before. How is it done?
Changing to ps makes no difference.
