Connection bit order between hierarchy

Hi,

I got unintended bit order of bus connection between SystemVerilog top with Block Design in lower hierarchy.

I intend to connect inst3 to out[3] but Quartus connected in reversed order.

Please see Technology map viewer screen shot and open archived project.

Is there any Quartus option to fix this problem?

This happens with (System)Verilog top only.
I already experiment bdf, tdf, vhd top instead of sv, they work as expected.
I am using Quartus Pro 23.2.

Thanks,
Masaru