Occasional Contributor
Super ContributorHave you tried running the simulation using the NativeLink simulation flow?
Without the design files, it is challenging to debug and understand the root cause. If possible, creating a simplified design would help us investigate further.
Otherwise, the currently identified possible root cause is described in the KDB below, which I believe you have already reviewed:
https://community.altera.com/kb/knowledge-base/fatal-sigfpe-floating-point-exception/342914
Regards,
Richard Tan
Occasional ContributorNo, I have not tried NativeLink simulation flow before. How is it done?
Changing to ps makes no difference.
Super ContributorNativeLink in Quartus is an automated simulation flow. It removes the need to manually compile and run simulation scripts.
You may checkout the user guide below:
https://docs.altera.com/r/docs/703090/21.1/questa-intel-fpga-edition-quick-start-intel-quartus-prime-standard-edition/specify-eda-tool-settings
There is an example design in the user guide (quartus-std-lite-pll-ram) to test it out. You can get the Quartus Pro version example design from the Pro version user guide. However, the simulation flow is by manually creating the simulation script.
https://docs.altera.com/r/docs/691278/21.3/questa-intel-fpga-edition-quick-start-intel-quartus-prime-pro-edition/questa-intel-fpga-edition-quick-start-intel-quartus-prime-pro-edition
If you can duplicate the issue by modifying the example design, do share with us the modified design (zip the .QAR file and attach in forum) for further investigate.
Regards,
Richard Tan
