Forum Discussion
zjj
Occasional Contributor
Occasional Contributorrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the t...
KennyT_altera
Super Contributor
Super ContributorCan you attached your design.qar file for investigation?
When you report the tuming that have -1.8ns recovery violation, are they using a different clock or same clock?
zjjOccasional Contributor
Occasional Contributoroh, sorry! launch clk and capture clk is not same clock.
