Forum Discussion
zjj
Occasional Contributor
Occasional Contributorrecovery timing issue
I am working on Agilex 7 FPGA with quartus 25.3 software. in my project, I use the asynchronous reset and sync de-asserted stragegies. and I add the rst synczer circuit for each sub module in the t...
sstrell
Super Contributor
Super ContributorGenerate a detailed slack/path report in the timing analyzer (Report Timing) to understand all the resources the paths that are failing are going through and post that report here (Data Arrival Path and Data Required Path).
zjj- KennyT_altera
Check the userguide again for the synchronizer, I remember you will need to set false path for different clock.
- zjj
launch clk and capture clk is synchronous ，and the two clock is from one pll! according to the following guideline, it suggest that use synchronous reset srategie instead of async reset?
https://docs.altera.com/r/docs/683539/25.1.1/an-917-reset-design-techniques-for-hyperflex-architecture-fpgas/asynchronous-reset-design-strategies
