Forum Discussion
Occasional Contributorrecovery timing issue
Super ContributorGenerate a detailed slack/path report in the timing analyzer (Report Timing) to understand all the resources the paths that are failing are going through and post that report here (Data Arrival Path and Data Required Path).
Occasional Contributor
- KennyT_altera
Check the userguide again for the synchronizer, I remember you will need to set false path for different clock.
- zjj
launch clk and capture clk is synchronous ，and the two clock is from one pll! according to the following guideline, it suggest that use synchronous reset srategie instead of async reset?
https://docs.altera.com/r/docs/683539/25.1.1/an-917-reset-design-techniques-for-hyperflex-architecture-fpgas/asynchronous-reset-design-strategies
- KennyT_altera
Even though both clocks are generated from the same source and have a fixed relationship, using an asynchronous reset can still lead to timing problems if the reset signal changes near a clock edge. This risk is specifically mentioned in the official guidelines.
Synchronous reset is safer and makes timing analysis much easier for design tools like Quartus Prime. It also ensures compatibility with advanced FPGA features such as Hyper-Registers, which do not support asynchronous reset.
