recovery timing issue

Even though both clocks are generated from the same source and have a fixed relationship, using an asynchronous reset can still lead to timing problems if the reset signal changes near a clock edge. This risk is specifically mentioned in the official guidelines.

Synchronous reset is safer and makes timing analysis much easier for design tools like Quartus Prime. It also ensures compatibility with advanced FPGA features such as Hyper-Registers, which do not support asynchronous reset.

Sorry for the late reply, i will get back to you by tommorow. 

Yes, you should use a synchronous reset strategy when your launch and capture clocks are synchronous and both come from one PLL.

This recommendation is directly supported by several sections of the document:

• Section 1.1.2: States that Hyper-Registers do not support asynchronous resets and explicitly recommends using synchronous resets when a clock is present during every reset assertion.
• Section 1.2.1.1: Explains that asynchronous resets can violate recovery/removal timing, even if both clocks are from the same PLL, so synchronous reset is safer.
• Section 1.2.2: Describes how synchronous resets make timing analysis simpler and more robust.
• Section 1.4.1.1: Recommends converting asynchronous resets to synchronous resets to take full advantage of device features.

In summary, these sections together support the clear answer: yes, use a synchronous reset for your described setup.