zjj
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in my project that base agilex7 fpga, I need to use bit mask memory. the bit mask memory rtl behavior as follow. as quartus only support byte mask memory, so I think quartus tool should use logic(ALM registers) implementation instead of M20K. However, the fitter technology map shows that the following rtl behaviors is mapping to the M20k, that cause rtl behavior is inconsistent with fitter netlist. is this quartus eda bug?
always @(posedge clk) begin
if (ram_wra) data[ram_addra] <= (data[ram_addra] ＆ ~ram_bwma) | (wrp_dina ＆ ram_bwma);
end
always @(posedge clk) begin
if (ram_rdb) wrp_doutb <= data[addrb];
end
