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zjj's avatar
zjj
Icon for New Contributor rankNew Contributor
9 hours ago

memory infer

in my project that base agilex7 fpga,  I need to use bit mask memory.   the bit mask memory rtl behavior as follow. as quartus only support byte mask memory, so I think quartus tool should use logic(...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
4 hours ago

Hi,

the code is describing read-modify-write action that can be basically implemented with M20K block ram. Due to synchronous operation ram_addra is evaluated in different cycles for read and write, shown simple behavioral code is possibly not working as expected.

Question is if you require write to different address every clock cycle, in this case pipelined implementation with Agilex quad port mode can achieve the required functionality. But I doubt that it can be simply inferred.

Regards Frank