Occasional Contributor
Super ContributorHi,
the code is describing read-modify-write action that can be basically implemented with M20K block ram. Due to synchronous operation ram_addra is evaluated in different cycles for read and write, shown simple behavioral code is possibly not working as expected.
Question is if you require write to different address every clock cycle, in this case pipelined implementation with Agilex quad port mode can achieve the required functionality. But I doubt that it can be simply inferred.
Regards Frank
Occasional Contributorso I am worry that logic function of the fitter netlist is inconsistent with rtl code behavior. how to verify it ? is there tool to verify the logic equivalence between netlist and rtl code?
