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New ContributorCDC Interconnect in Platform Designer
Hello community,
I have several custom DSP blocks that expose an AXI4-Lite CSR interface for system control and monitoring. These registers need to be accessed from the HPS (bare-metal/Yocto) via the H2F lightweight AXI bridge. The H2F LW bridge operates on a 100 MHz clock, while the AXI4-Lite interfaces inside the DSP blocks are synchronous to a separate DSP clock that is asynchronous to the 100 MHz domain.
I am currently using the Intel AXI interconnect in Platform Designer to connect the LW bridge to the DSP blocks, and I’ve observed that No clock-domain crossing logic is being inserted between the LW bridge and the DSP AXI interfaces.
My question is: does Platform Designer provide an interconnect mechanism (similar to Xilinx AXI interconnects) that allows connecting AXI master and slave interfaces in different clock domains and automatically handles the required CDC logic? Or is explicit CDC handling required at the AXI slave interface level for this use case? Any guidance or best practices would be greatly appreciated.
6 Replies
- RichardT_altera
Super Contributor
Yes—Platform Designer can automatically handle CDC between interfaces, including AXI.
You may checkout the user guide below:
https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/reducing-logic-utilization-with-multiple-clock-domains
Regards,
Richard Tan 
sstrellIt should. Where are you seeing that no clock crossing logic is being added? Have you generated the system and gotten an error or warning?
YZhou98Hi, I connected the 100MHz clock source to the HPS bridge interfaces.
Then, I connected the 100 MHz clock and its sync reset to the slave interface of the AVMM clock crossing bridge intel IP and the DSP clock to the master interface (https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/avalon-memory-mapped-clock-crossing-bridge-intel-fpga-ip).
Finally, I connect the master interface of the AVMM CDC IP to the slave interface of the AXI bridge Intel FPGA IP and export the master to the top level.
Is this a legal PD design?
- RichardT_altera
Looks legal. As long as Platform Designer shows no warnings and the clock/reset domains are handled correctly, this should be a valid design.
Regards,
Richard Tan
