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YZhou98's avatar
YZhou98
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8 months ago

CDC Interconnect in Platform Designer

Hello community, I have several custom DSP blocks that expose an AXI4-Lite CSR interface for system control and monitoring. These registers need to be accessed from the HPS (bare-metal/Yocto) via th...
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sstrell's avatar
sstrell
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8 months ago

It should.  Where are you seeing that no clock crossing logic is being added?  Have you generated the system and gotten an error or warning?

YZhou98's avatar
YZhou98
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7 months ago

Hi, I connected the 100MHz clock source to the HPS bridge interfaces.

Then, I connected the 100 MHz clock and its sync reset to the slave interface of the AVMM clock crossing bridge intel IP and the DSP clock to the master interface (https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/avalon-memory-mapped-clock-crossing-bridge-intel-fpga-ip). 

Finally, I connect the master interface of the AVMM CDC IP to the slave interface of the AXI bridge Intel FPGA IP and export the master to the top level.

Is this a legal PD design?

 

  • RichardT_altera's avatar
    RichardT_altera
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    7 months ago

    Looks legal. As long as Platform Designer shows no warnings and the clock/reset domains are handled correctly, this should be a valid design.

    Regards,
    Richard Tan

    • RichardT_altera's avatar
      RichardT_altera
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      7 months ago

      Let me know if further assistance is required.

      Regards,
      Richard Tan

      • YZhou98's avatar
        YZhou98
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        7 months ago

        Thanks, it looks good for now.