CDC Interconnect in Platform Designer

Hi, I connected the 100MHz clock source to the HPS bridge interfaces.

Then, I connected the 100 MHz clock and its sync reset to the slave interface of the AVMM clock crossing bridge intel IP and the DSP clock to the master interface (https://docs.altera.com/r/docs/683609/25.1.1/quartus-prime-pro-edition-user-guide-platform-designer/avalon-memory-mapped-clock-crossing-bridge-intel-fpga-ip). 

Finally, I connect the master interface of the AVMM CDC IP to the slave interface of the AXI bridge Intel FPGA IP and export the master to the top level.

Is this a legal PD design?